ISOW7841: ISOW7841 breaks down
Part Number: ISOW7841
Hello, this topic is a continue of a previous one ISOW7841: ISOW7841 breaks down
The same customer has some additional questions:
1. In TIDA-00300 design the output of ISOW7841 is protected by zener diode. But such solution is not described in data sheet. Is it mandatory to place a zener diode to protect ISOW7841?
2. In customer's application ISOW is used for different interfaces (485, CAN, RS-232).
The current consumption from internal voltage converter of ISOW is not continuous, but changed in a pulsed way, because of used interfaces specialities.
Unlike TIDA-00300, customer's design does not contain an LED on ISOW output. This LED acts also as a passive load for internal power converter in ISOW.
Could be happen, that these two factors (pulsed current, lack of additional passive load) can lead to voltage increasing, when interface stops to consume the current?
Thanks for reaching out to us. Please find below my inputs.
Pulsed current is not going to be a problem for ISOW, the current need not necessarily be continuously drawn.
The passive load is also not a mandatory requirement if the suggestions provided in Andrey's E2E post are followed.
We don't expect the pulsed current operation and lack of passive load to cause any overvoltage problems. The overvoltage issue can occur if the primary supply of iSOW VCC, goes through brown-out while the secondary side supply VISO stays above its UVLO. Such test condition may result into sync issues between primary and secondary dice thereby leading to an open-loop operation eventually resulting into output overvoltage condition. Thanks.
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In reply to Koteshwar Rao:
Customer upgraded his board:
- 1000uF capacitor on VCC rail is added
- 1uF capacitor, 470R resistor and zener diode are added in parallel to VISO bus
Then customer performed a power cycle tests with watching for VCC(blue) and VISO(yellow).
As we can see on the scope below:
- in some cases after VCC is applied (blue), VISO(yellow) starts to increase
- increasing of VISO(yellow) happens, while VCC voltage stays stable(blue)
In reply to Slava Prokopii:
Thank you for sharing the update with waveform.
Could you please confirm the capacitors used at VISO pin? I see you mentioned that customer added 470Ω resistor, Zener and 1µF capacitor. Is this in addition to the capacitors that were already existing? Could you please confirm what were the already existing capacitors?
VCC & VISO need a min of 10µF + 0.1µF as close as possible to the pins on the same PCB layer as device. Any value less than 10µF + 0.1µF will make the device not operate normal. That's why I needed a confirmation on this.It is suggested to use an additional 100µF at VCC to avoid any overvoltage issue due to power cycle tests. Please do also point out where exactly was the 100µF capacitor placed on customer PCB? Any pictures showing the placements would also be helpful.
Please do confirm that these suggestions for capacitor values and their placement are followed. Thanks.
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