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Part Number: ISO1541
Having Issues with the Slave side clock disappearing at the output side (Side 2) of our ISO1541. Master is a Xilinx FPGA connected to Side 1 of the ISO1541, Slave is a Delta Power Supply. We are trying to perform PMBus operations and are unfamiliar with PMBus though it seems I2C/SMBus are the PHY layer of the comm link.
It seems that the Clock disappears from the output of the ISO1541 after the slave ACKs a transaction. Below is a scopeshot of the Controller side SDA, SCL and the Slave side SCL.
Could this be the slave stretching the clock? I've never come across clock stretching so am unfamiliar with it.
Thanks for the help
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In reply to Anand Reghunathan:
Thanks for the quick reply. To confirm your suspicions, we are operating the bus at 100K and have confirmed this bus speed with the PSU datasheet. The PSU Mfr, has also confirmed that the unit will throttle the clock "if there is a mismatch between the system clock and the psu". Not sure what is meant by "a mismatch" between clocks. However, PMBus is somewhat strange, in that the I2C format is not
[Start][Device Address][R/Wn][ACK][Register Offset][Stop] [Start][Device Address][ACK][Data1][Data2]...[DataN][Stop]
Instead, [Register Offset] is replaced by [Command]. Where in a PSU I imagine a [Command] could be, Read an ADC to get a Thermistor Measurement or some other such thing that may take longer than just spitting out the contents of a memory location. Thus, the need for clock stretching on the slave's end.
We are going to try and switch out the ISO1541 with the ISO1540 which has the Bidirectional Clock to see if this will remedy our problem.
I've uploaded a snippet of the schematic pertinent to this issue in both a .jpg and .png formats. For some reason it doesn't preview.
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