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What is fail-safe biasing, and how do you design for it?
In order to comply with RS-485 standards, the receiver output must generate a logic level high when the differential input (VID) is more than 200mV, and must output a logic level low when VID is less than -200mV. However, you can generate an invalid output under three scenarios:
In any of these scenarios, for a terminated transmission line, the RS-485 receiver VID would be zero and a non-fail-safe receiver output would be indeterminate.
Fail-safe biasing provides a differential voltage to the idle bus in order to maintain the receiver at a logic high level. If you don’t take fail-safe biasing into account, the termination resistors can lower the bus voltage to 0V, leading to an incorrect output or signal oscillation. You can design fail-safe biasing by using a resistor network along with an RS-485 transceiver. TI’s isolated RS-485 transceivers all have integrated fail-safe basing ] for open, short or idle bus situations, eliminating the need for external circuitry to achieve this functionality.
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