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ISO1540: ISO1540 inverted pedestal voltage floating

Kuan Wei Chen (Kevin Chen)
Genius 9710 points
Part Number: ISO1540

Dear Team,

My customer is using NXP's PCA9617ADPJ, and there facing inverted pedestal voltage floating issue.

Will our product has the same issue?

Because I check us datasheet also have similar waveform:

BR

Kevin

  • 0
    TI__Mastermind 49445 points
    Hi Kevin,

    One of the common approaches used to implement bidirectional channels for I2C application is to raise the VOL at one side of I2C device to avoid closed loop lockout. This has been described in detail in Section 8.4 of ISO154x datasheet.

    Such implementation will lead to the behavior that you have referred as inverted pedestal in your post. Hence you will notice similar behavior with ISO154x Side1 as well while Side2 will not have such behavior.

    Let me know if you have any other questions, thank you.


    Regards,
    Koteshwar Rao
  • 0 in reply to Koteshwar Rao
    TI__Genius 9710 points
    Dear Rao
    Thanks for quick reply.
    1. What is close loop lockout?
    2. Your VOL means supply voltage VCC1 and VCC2?
    3. Base on the figure.26. Is it means from SDA2 to SDA1 won't have this kind of issus but from SDA1 to SDA2 is depend on load condition? Why?
    BR
    Kevin
  • 0 in reply to Kuan Wei Chen (Kevin Chen)
    TI__Mastermind 49445 points
    Hi Kevin,

    Please find below my inputs.

    1. As shown in Page 1 of ISO154x datasheet, the bidirectional channel is formed using two unidirectional channels. If two identical unidirectional channels are connected back without any additional circuit, then the circuit locks down to logic LOW state and doesn't respond to any external input.
    Since output of one unidirectional channel is fed as input to another unidirectional channel, a LOW state at one output will make the other channel output also LOW. Since both inputs and outputs are LOW, any external HIGH input will not change the state of the channels. This is called closed-loop lockout/latch-up. To avoid such lockout, ISO154x breaks the closed-loop by raising VOL on Side1 higher than its VIL. This is achieved by adding a diode as shown in the diagram on Page 1 of ISO154x datasheet.

    2. VOL on Side1 is raised slightly higher than VIL of Side1. This means that both SDA1 & SCL1 have higher VOL compared to SDA2 and SCL2. Hence the VOL I am referring is on VCC1 side.

    3. Your understanding is correct that you will notice this behavior at SDA1 when data is transmitted from SDA1 to SDA2 but its occurrence doesn't depend on load, this behavior will be observed at SDA1 all the time when there is data transmission from SDA1 to SDA2.
    The reason for such behavior is explained in detail in section 8.4.2 of ISO154x datasheet along with relevant references to figures and block diagram. Please go through this section and let us know if you still have any questions. Thanks.


    Regards,
    Koteshwar Rao
  • 0 in reply to Koteshwar Rao
    TI__Genius 9710 points
    Dear Koteshwar Rao

    Thanks a lot!!