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ISO1410: Communication error when noise testing

Part Number: ISO1410

Hello support team,

I have some questions about the isolated RS-485 transceiver ISO1410.

Our customer is considering adopting ISO1410 currently, .
When noise is applied in the electrical fast transient / burst immunity test (IEC61000-4-4), the communication error occurs in RS-485 communication.
The test conditions are as follows.
・ electrical fast transient / burst immunity test (IEC61000-4-4)
・ Mode: Common mode
・ Voltage: -4 kV
・ Frequency: 5 kHz and 100 kHz
・ GND1 is connected to the power line, GND2 is used close to the communication line (FG)
The specifications of RS-485 communication are as follows.
・ Data rate: 38400bps
・ Type: Half-duplex
Immediately after applying noise in the electrical fast transient / burst immunity test, the receiver output R of ISO1410 is forced high level for about 100 μs regardless of the state of the differential bus signal.
 
[Question]
1. The customer guesses that the cause of the above phenomenon is a malfunction of the “Glitch-Free Power up Power Down function”.
Is his opinion correct?

2. If the answer to question 1 is "Yes",
2-1. Which does "Glitch-Free Power up Power Down" function work on the circuit, Vcc1 side or Vcc2 side?
2-2. How does the internal circuit behave when "Glitch-Free Power up Power Down" is malfunctioning?
2-3. Is there a recommended circuit to prevent the mulfanction of "Glitch-Free Power up Power Down"?

3. If the answer to question 1 is "No",
3-1. What are the possible malfunction factors?

4. As a noise countermeasure, the customer is considering putting about 1000pF of a ceramic capacitor between the differential signals lines (A and B). Does adding a capacitor interfere with the operation of this IC?

Sincerely,
M. Tachibana

  • Hi Tachibana-san,

    To achieve Class A performance (no communication errors) for ±4-kV IEC61000-4-4 EFT tests, system design is critical. Does our customer mind sharing schematic and PCB files for analysis? This may be done privately separate from this page.


    Thank you,
    Manuel Chavez

  • Hello Chavez-san,

    Thank you for your reply.

    We are trying to get a schematic and PCB layout from the customer.
    The customer hopes to share the information separately from E2E.
    We'd like to send these data to your privately, so could you tell me your e-mail address?

    Sincerely,
    M. Tachibana

  • Hi Tachibana-san,

    I have sent you a request to connect, so we can communicate privately through E2E's Personal Messages. This thread will be updated with general notes throughout the debug.


    Thank you,
    Manuel Chavez

  • Hi Chavez-san,

    Thank you for your reply.
    I just contacted you via a E2E private message.

    Sincerely,
    M. Tachibana

  • Hello Tachibana-san, all,

    Schematic and layout reviews are pending. In the meantime I have shared schematic and PCB considerations with Tachibana-san to achieve Class A 4-kV IEC61000-4-4 EFT test pass:

    • Possible solutions rest on improving the schematic or PCB layout. Class A operation is the most sensitive to layout techniques
    • Adding a capacitor across the differential bus lines will not be very helpful to pass, but including small capacitances on each bus line to GND can help - specific capacitance value vary based on datarate and acceptable RC
    • Specific design considerations for high immunity and protection are found in the following TI Designs - TIDA-01401 and TIDA-00731

    Please feel free to reply and follow up or ask questions regarding the documents linked above, or you may create a new thread using the red and yellow buttons in the top right corner of this window.


    Thank you,
    Manuel Chavez

  • Hello Chavez-san.
    I am very grateful for your kind support.

    As I informed you, TI-Japan engineers are investigating in parallel.
    We will share the information you provided with him.

    Temporarily, I'll put this thread in resolved status.

    Sincerely,
    M. Tachibana