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ISOW7843: Viso voltage failure

Part Number: ISOW7843

Hello, I have some inexplicable failures of ISOW7843 in my SCB microcontroller board.

Three SCB boards are installed on a rack and each board receives the same power supply power-good signals from three power supply boards. The same open-collector input signal is connected to three ISOW7843 on three different boards.

Each isolator input has a pull-up resistor to its isolated VISO voltage.

Sometimes (with a very low frequency), after a power-up, a failure is detected during the system autotest on ISOW7843 device; perhaps the failure could also occur during power-down but we can detect it only at next power-up.

When a ISOW7843 fails its VISO is permanently shorted with GND2.

The selected VISO for the device is 3.3V through a 1K resistor on the SEL pin; this resistor is in disagree with the device datasheet. For VISO at 3.3V, a short circuit of SEL pin to GND2 is recommended.

So my question is: can this resistor cause the failure with the short circuit between VISO and GND2 pins?

We can change the 1k resistor with a 0 ohm one but with so a low frequency failure we can't be sure the problem is solved.

Thank you in advance for your response.

Silvano

  • Hi Silvano,

    Welcome to E2E! The 1kΩ resistor can influence this failure; please do short the connection from SEL to GNDISO.

    Adding a 100uF capacitance on Vcc can also help prevent this failure from occurring. Have any waveforms of Viso during this failure been captured or surrounding devices damaged?


    Respectfully,
    Manuel Chavez

    Update: This thread was correct to recommend a short-circuit connection from SEL to GNDISO, not Viso.

  • Hi Manuel,

    the input and output bypass capacitors are present according to the datasheet as shown in next fig

    Unfortunately the probability to acquire data on the device that will fail is near to zero. We have a rack with three board and two isolators each; before to have a fail we must power on and off the rack about 100 times. This fail arises from the field because many racks are already installed and sometimes a fail is observed.

    I have some acquisition on devices that doesn't have fail. In next figure an acquisition during a power-off:

    • Ch 1 (Yellow): Viso
    • Ch 2 (Blue):       Digital input signal (NOK24)
    • Ch 3 (Fuchsia): Viso (on the second device)
    • Ch 4 (Green):   Digital input signal (on the second device)

    Power-off occurs on Ch2 (Blue) edge due to general power supply loss; this digital input returns slowly to ground while the power supply capacitors are disharging. The Viso voltages of ISOW7843 remain high until the input voltage 3.3V is off and the bypass capacitors disharged.

    After your response we decided to modify the board changing the SEL pin resistor to 0 ohm; after this we have to do a lot of power-off test.

    Thank you a lot for your prompt reply

  • Hi Silvano,

    Thank you for sharing this schematic and power down waveforms. I understand these are for non-failing units and the issue takes many iterations to repeat, but please do consider adding the 100uF capacitance to Vcc input voltage pin for these tests as recommended in Section 11 of the ISOW784x datasheet:




    Best,
    Manuel Chavez

  • Hi Manuel,

    thank you for your answer; this will probably solve the problem but since we have to modify all the boards and then tests them for a few days, I'll let you know the outcome as soon as we finish.

    Best regards

    Silvano Rossi

  • Silvano,

    You're welcome! We will await your updates.


    Thank you,
    Manuel Chavez

  • Hi Silvano, all,

    I apologize for the mistake, but my original response has been corrected to recommend a short-circuit connection from SEL to GNDISO to achieve Viso = 3.3V operation. Please let me know if there are any concerns.


    Thank you,
    Manuel Chavez