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  • TI Thinks Resolved

L2SRAM/Cache/Program and Platform Files?

Genius 3270 points

Replies: 4

Views: 3803

I've been starting to think about how we want to use caching for our new project using AM5728 and SysBios.  Since we will have a very large project we will have to load the code in External RAM.  My thought was to allocate all cache possible in L1 and L2.  However, not all L2 is cacheable, so that will leave a small amount of L2 available for general use.

I updated my platform as shown below.

My linker.cmd file generated shows:

MEMORY

{

OCMC_RAM2 (RWX) : org = 0x40400000, len = 0x100000

OCMC_RAM1 (RWX) : org = 0x40300000, len = 0x80000

OCMC_RAM3 (RWX) : org = 0x40500000, len = 0x100000

L2SRAM (RWX) : org = 0x800000, len = 0x40000

EXT_RAM (RWX) : org = 0x80000000, len = 0x80000000

}

I guess I am surprised that the L2SRAM len is 256 KiB.  On the AM5728 the L2 SRAM is 288-KiB.  256KiB can be cache leaving 32 KiB for SRAM.  I guess I expected the L2 Cache setting of 256k to reduce the L2SAM available by 256k and in this case leave 0.  So, I guess the L2SRAM under Custom Memory needs to be manually coordinated with the L2 Cache pulldown.  True?

If that is the case, does the cache use the lower part or upper part of the memory?

In other words do I want

L2SRAM 0x00800000 0x00008000  <- 32KiB starting at 0x800000

or

L2SRAM 0x00840000 0x00008000 <- 32KiB starting at 256KiB above 0x800000

  • Not sure why my picture didn't post.  Here it is again....

  • I tried to do the same and have come to the conclusion that the Platform editing "wizard" (dialog box) does not appear to be working correctly.  After much wrangling, reverting back to the original, and re-wrangling I was able to set the L2 cache size to 256k and see the L2SRAM size as 0, but "Finish"ing the dialog box produces a platform that's very different from the original one and doesn't seem to be usable. This dialog is *supposed* to adjust the internal RAM sizes based on your chosen cache sizes but it's not working.

    If you don't need to have the linker place anything into L2SRAM, the easiest work-around would be to use the AM572x platform as-is from the product (with L2SRAM as size 0x40000 and L2 cache size as 0k) and change the cache size at run-time with the ti.sysbios.family.c64p.Cache module.  As long as you don't specify L2SRAM as the placement for any code/data/stack then nothing will be linked to there and you would be able to change the size to 256k at run-time in your program.

    If you want to actually change the platform itself during build-time, there is a way to do that by way of a "config.bld" file that you add to your CCS project, where you redefine the platform's customMemoryMap and l2Mode, but I would need to know your starting platform.  If you'd like to explore this possibility, let me know the platform that you're using.

    Christopher Peters

    If that is the case, does the cache use the lower part or upper part of the memory?

    In other words do I want

    L2SRAM 0x00800000 0x00008000  <- 32KiB starting at 0x800000

    or

    L2SRAM 0x00840000 0x00008000 <- 32KiB starting at 256KiB above 0x800000

    I'm having trouble finding the exact answer for this.  In general, the cache occupies the upper part of the L2SRAM, so the RAM portion will always start at the bottom of the cache/RAM block.  But for AM572x, where the C66 DSP contains 288KB of L2SRAM, the extra 32KB in addition to the 256KB block is always RAM, and I would assume that the always-RAM 32KB block starts above the cache/RAM block (i.e., at 0x00840000 -> 0x00848000).  Regardless, we can know that if you don't configure the whole 256KB cache then the RAM portion starts at 0x00800000.

    Regards,

    - Rob

  • In reply to Robert Tivy:

    Thank you Robert for that very detailed look at my question and glad I'm not going crazy. LOL

    Anyway, it is too early in our design to know if we will need anything in L2SRAM, but I wanted to have that option. One thing I was thinking of using it for is transferring data from an FPGA via PCIe. We will need a high data throughput, so I was thinking of having the inbound PCIe transfers go to L2SRAM for more processing.

    Our custom board is based on the AM5728EVM GP. I started the above example with the evmAM572X platform file.

    Maybe I should have custom memory in two pieces, L2CACHE 0x800000 0x40000 with cache size 0, and then have L2SRAM as 0x840000 0x8000. Then use the cache module on the L2CACHE segment. (Not that I know how to do that yet.)
  • In reply to Christopher Peters:

    For the benefit of the E2E knowledge base I'm replying with some new information regarding this thread, courtesy of a dedicated TI employee...

     

    Cache always grows from the bottom of the L2 memory for C66x DSP. When cache size is set to 256kb L2 memory, (0x00800000 to 0x00808000 – 32kb) will be configured as SRAM and remaining as cache.

    Here is the behavior of C66x DSP cache,

     

    TMS320C66x DSP Cache -  http://www.ti.com/lit/ug/sprugy8/sprugy8.pdf

    cid:image001.png@01D3CFE0.19C54920

    We tried this and confirmed that initial 32kb of the memory is configured as SRAM. Can you update your post with this observation for benefit of others on E2E?

     

    Regards,
    Shyam

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