Cio Input/Output Capacitance JEDEC – no definition offered TI – The capacitance of an input/output (I/O) terminal of the device with the input conditions applied that, according to the product specification, establishes the high-impedance state at the output. This parameter is the internal capacitance encountered at an input/output (I/O) of the device. The values that are given are not production-tested values. Normally, they are typical values given for the benefit of the designer. These values are established by the design, process, and package of the device. This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036
Cio Input/Output Capacitance
JEDEC – no definition offered
TI – The capacitance of an input/output (I/O) terminal of the device with the input conditions applied that, according to the product specification, establishes the high-impedance state at the output.
This parameter is the internal capacitance encountered at an input/output (I/O) of the device. The values that are given are not production-tested values. Normally, they are typical values given for the benefit of the designer. These values are established by the design, process, and package of the device.
This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036
As a circuit designer and board designer, how am I to use the input and output capacitance of a digital I/O device? I know that a higher capacitive load affects timing. But what other considerations (all of them) do I need to be aware of when connecting digital (CMOS/TTL) devices (processors, FPGAs, etc) as it pertains to Cin and Cout?
Hi Tom
Cin and Cio are parameters that can be used for many calculations and modeling purposes, but the most common use and most important use is to insure the part meets datasheet spec in your system. It is very simple. The part will be specd into a specified load. It will meet specs driving that capacitance or lower. Using the Cin you can determine how may parts you can drive and still be in spec. If your part is specd to drive 30pf then it could drive 3 parts with 9pf loads and still meet spec
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Thanks for the quick response and the information!
If the load capacitance is larger than what the driver can handle, will the output become unstable (like an op-amp driving into a large-C load)?
I see that you had 3 loads, 9pF each, implying a certain amount of capacitance left over for 1) margin, and 2) board trace capacitance.
You said that it is used for many calculations and modeling purposes. Again, as a board designer, what modeling and calculations (besides the one we have talked about) should I also look at? In other words, what are the top 5 types of calculations a board designer would do with Cin and Cout (besides making sure the driver can drive the load capacitance)?
Thank you for your help!!
I am not a modeler so I cant help much with modeling questions.
too much capacitance will not usually make logic devices unstable. most of our logic can drive more capacitance than specd but they may not meet the datasheet limits.
More capacitance on the load will slow down the edges. Prop delays will slow down. Max frequency will decrease, low level may rise and high leve may decrease.
So too much capacitance will move the output in between a high level an low level which might cause problems on the next part down the line.
Here are some basic model comments. dont know much more.
IBIS models, you would coose the capacitance closest to the actual load and run the model.
SPICE models would have CIn and Cout of the various parts already in the model so you would just give it board parameters and run it.