Delta VT Hysteresis (VT+ – VT–)

DVT (Delta) Hysteresis (VT+ – VT–)

JEDEC – The difference between the positive-going and negative-going input threshold voltages.

TI – Refer to the JEDEC definition above.

Hysteresis has been incorporated into logic devices for many years and exists in bipolar as well as CMOS circuitry. Although the circuitry is different, the implementation is the same: the input voltage threshold actually changes internally from one level to another, as the input logic level itself switches. The Figure below is the most common voltage plot for the input and output, as the input transitions from one logic state to the other. The next Figure, however, shows VIT+ and VIT– in a voltage vs time waveform.

The benefit of a device that has built-in dc hysteresis is that, depending on the amount of hysteresis and the amount of noise present, the input is immune to such noise. This digital form of filtering out unwanted noise can be beneficial in a system where noise caused by electromagnetic interference (EMI) or crosstalk cannot be reduced. The next two Figures  conceptually depict the functionality of hysteresis.

 

This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036).  To download the full PDF version of this application report, please use the following  URL:  http://www.ti.com/lit/szza036