VO Output Voltage

JEDEC – The voltage at the output terminals.

TI – The range of output voltage levels over which the logic element is specified.

VO min and max values are used as test conditions for IOZH and IOZL. See these tests for details.

Helpful Hint:

The load at the output strictly determines the output voltage. As discussed in the VOH and VOL descriptions, a constant dc current decreases and increases, respectively, the output voltage. For this reason, it is not recommended to drive bipolar inputs with CMOS outputs unless the sum of all bipolar input current is less than the rated IOH and IOL of the CMOS output. Highly capacitive loads, such as any CMOS type input, will not incur any static dc current, so a CMOS output voltage should be close to the rail when asserted high or low. Capacitive loads, not the ultimate static dc voltage level, determine the time it takes for the output to arrive at the logic high or low state.


This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036).  To download the full PDF version of this application report, please use the following URL:  http://www.ti.com/lit/szza036