VI Input Voltage
JEDEC – The voltage at the input terminals.
TI – The range of input voltage levels over which the logic element is specified to operate.
VI min and VI max values are used as test conditions for the II, ICC, DlCC, Ci, and Cio test. See those specifications for details.
If there are clamp diodes between the device inputs and the VCC supply (see Figure below) for ESD protection or overshoot clamping, the positive absolute maximum rating for the input voltage will be specified as VCC + 0.5 V. Keeping the applied input voltage less than 0.5 V above VCC ensures that there will not be enough voltage across the clamp diode to forward bias it and cause current to flow through it.
You may exceed the negative rating if you ensure that you are not putting too much current through the ground-clamp diode. The maximum current that you may put through the ground-clamp diode is specified in the IIK absolute-maximum rating.
This parameter provides a means to determine if the device is tolerant of a higher voltage than the supply voltage. If the input is overvoltage tolerant, the positive maximum rating for the input voltage will be an absolute voltage rating (e.g., 5.5 V) and will be limited by the capabilities of the wafer-fab process. For example, the LVC technology is specified to operate at a voltage supply no higher than 3.6 V. However, the input voltage is recommended to be 5.5 V maximum. This indirectly states that the device is a 5-V tolerant device. The same can be said about AUC devices because the maximum supply voltage is 2.7 V, whereas the maximum input voltage is 3.6 V, making this technology 3.3-V tolerant.
This parameter explicitly states the recommended minimum and maximum input voltage levels for any input. While the VI specification typically spans the range from below ground to above VCC, failure to supply a voltage to the input of a CMOS device that meets the VIH or VIL recommended operating conditions can cause: (1) propagation of incorrect logic states, (2) high ICC currents, (3) high input noise gain and oscillations, (4) power- and ground-rail surge currents and noise, and (5) catastrophic device and circuit failure.
This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036
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