tPZH Enable Time (of a 3-State Output) to High Level JEDEC – The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined high level. TI – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined high level. This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined high level. Output enable time, tPZH, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a high logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZH, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pulldown resistor to obtain a valid logic-low level when the output is in the high-impedance state. tPZL Enable Time (of a 3-State Output) to Low Level JEDEC – The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined low level. TI – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined low level. This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined low level. Output enable time, tPZL, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a low logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZL, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pullup resistor to obtain a valid logic-high level when the output is in the high-impedance state. This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036
tPZH Enable Time (of a 3-State Output) to High Level
JEDEC – The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined high level.
TI – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined high level.
This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined high level. Output enable time, tPZH, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a high logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZH, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pulldown resistor to obtain a valid logic-low level when the output is in the high-impedance state.
tPZL Enable Time (of a 3-State Output) to Low Level
JEDEC – The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined low level.
TI – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined low level.
This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined low level. Output enable time, tPZL, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a low logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZL, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pullup resistor to obtain a valid logic-high level when the output is in the high-impedance state.
This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036