th Hold Time JEDEC – The time interval during which a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal. TI – The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input. NOTE: 1. The hold time is the actual time interval between two signal events and is determined by the system in which the digital signal operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is to be expected. NOTE: 2. The hold time may have a negative value, in which case, the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit is to be expected. Hold time is tested by holding an input at a fixed logic level for the specified time after the transition of the other input (see Figure below). The device passes if the outputs switch to their expected logic levels and fails if they do not. Hold times are not checked simultaneously with other inputs or other recommended operating conditions. For additional information about hold time, refer to the TI application report; Metastable Response in 5-V Logic Circuits, literature number SDYA006. tsu Setup Time JEDEC – The time interval between the application of a signal at a specified input terminal and a subsequent active transition at another specified input terminal. TI – The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal. NOTE: 1. The setup time is the time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is specified. NOTE: 2. The setup time may have a negative value, in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation of the digital circuit is specified. Setup time is tested by switching an input to a fixed logic level at a specified time before the transition of the other input (see Figure below). The device passes if the outputs switch to their expected logic levels and fails if they do not. Setup times are not checked simultaneously with other inputs or other recommended operating conditions. For additional information about setup time, refer to the TI application report, Metastable Response in 5-V Logic Circuits, literature number SDYA006. This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036
th Hold Time
JEDEC – The time interval during which a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal.
TI – The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input.
NOTE: 1. The hold time is the actual time interval between two signal events and is determined by the system in which the digital signal operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is to be expected.
NOTE: 2. The hold time may have a negative value, in which case, the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit is to be expected.
Hold time is tested by holding an input at a fixed logic level for the specified time after the transition of the other input (see Figure below). The device passes if the outputs switch to their expected logic levels and fails if they do not. Hold times are not checked simultaneously with other inputs or other recommended operating conditions. For additional information about hold time, refer to the TI application report; Metastable Response in 5-V Logic Circuits, literature number SDYA006.
tsu Setup Time
JEDEC – The time interval between the application of a signal at a specified input terminal and a subsequent active transition at another specified input terminal.
TI – The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal.
NOTE: 1. The setup time is the time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is specified.
NOTE: 2. The setup time may have a negative value, in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation of the digital circuit is specified.
Setup time is tested by switching an input to a fixed logic level at a specified time before the transition of the other input (see Figure below). The device passes if the outputs switch to their expected logic levels and fails if they do not. Setup times are not checked simultaneously with other inputs or other recommended operating conditions. For additional information about setup time, refer to the TI application report, Metastable Response in 5-V Logic Circuits, literature number SDYA006.
This tutorial is based on the Understanding and Interpreting Standard Logic Data Sheets application report (SZZA036). To download the full PDF version of this application report, please use the following URL: http://www.ti.com/lit/szza036