Good Afternoon Team,
I am looking for a tri-state buffer for my SYNC CLK on the TPS54418. I want to be able to remove the clock input with high Z output on the buffer. I tried the SN74LVC1G126 but, it seems that that even with the buffer disabled (high Z output) the input clock has an effect on the output, see the plot below. This effect seems to be causing my SW node of my TPS54418 to change frequency slightly but rapidly.
Is there another part that will not allow the input clock to effect my output of my buffer, once the device is in high impedance?
yellow = buffer output, red = buffer input, SN74LVC1G126 disabled (high Z).
Condictions: 5Vcc, 0V - 4V square wave clk, 700kHz, output disabled.
This is what I am trying to do.
Did you try to use a pull down resistor at the output with lower resistance? 182 kOhm is a very large value. If I just guess the capacitance between input and output pin with 0.1 pF, we will get an impedance of 1/(2*pi*700k*0.1p)=2.27 MOhm at 700 kHz. Hence the tristate output will follow the input because of capacitive coupling. I'd suggest to try it with a 10 kOhm pull down resistor and to compare the results afterwards.
Best regards,Edwin Krasser
Thanks for the help!
Unfortunately, the 182K has to stay because, when I turn the clock off and the buffer is in high impedance mode, the resistor has to set the current through the RT/CLK pin of my TPS54418. Once the clock is no longer detected by the device the PLL in the TPS54418 is turned off and the RT resistor, (182k), is used to determine the switching frequency of the device.
Is there a device that would work better than the SN74LVC1G126? My goal frequencies are between 300kHz and 2MHz.
I think you will always face the same problem. But how about the double gate version SN74LVC2G126? Use the first gate to turn off the clock signal (with a lower pull down resistor) and the second with the 182 kOhm pull down.
in -----| \------| \---- out
| / | | / |
|/ 10k |/ 182k
| | | |
| GND | GND
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