Could you please confirm what is Q0 state in SN74LVC2G74 D Flip Flop. I have connected logic high to D, PRE/ & CLR/ and Clk is Low. Once clk is rising the Q will be high. But i am not able get what is the status of Q0 when clk is low. Is it intermintant state? looking for quick response.
Thanks and Regards Manikandan
. Q will always be opposite of Qbar. When clock is low the data on the Qpins will remain the same until next rising edge of clock.
Thanks for your quick response.
I agree with you. but my question is something different.
In datasheet from function table, i could see when PRE/, CLR/ - High and Clk-Low, D-X the output is Q0 and Q0/.
I would like know what it means or voltage levels.
Thanks and regards Mani
Qo simply means the data is latched into last state. It will not change from last clock data . If you clocked a high in previously then Q will be High or approx Vcc and Qbar will be low or gnd.
Thank you so much Chris. I got the point.
I need some more clarification. It is related to my application.
When the device is powered up with PRE/, CLR/ - High and Clk-Low, D-High, what will be the status of Q0?
the state is not defined after power-up.
it depends how the signals rise. imagine the power-up like a race condition. every circuit with sequential logic needs to be brought to a defined state first. but you can expect Q0 to have opposite level of Q0* - always in case of this example.
Where can be found CAD (Eagle) files for Little Logic components like SN74LVC1G74?
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