Hi, I am unsure how the ioff partial power down mode works. Is it automatic upon removal of the power supply, the ioff circuit protects the device from voltages on the output lines. Does Vcc need to be at ground, or can it be floating. Also can the inputs be floating in the power down state. In essence if i disconect the cable which supplies the signals to the buffer, including the supply, will it enter the power down mode, and be safe against voltages on the output side of the buffer.
Ioff works when the Vcc is at 0V. If Vcc is at 0V then voltages are allowed on the inputs and outputs. If the power is off (at 0V) then the inputs can float.
Does this also mean that during power-up there will not be any glitches on the output of the gate? I am looking for logic gates that will have no glitches during power-up. The power rails can't be guaranteed to be reliable, but the logic is going into gate drives, so to prevent shoot-through they must be glitch-free. Specifically, if I put a pull-down resistor on the output of an AND gate with the Ioff feature, and Vcc comes up on the gate, will the gate output glitch at all?
The Ioff feature works until about 0.5V. After that the output could begin to rise with Vcc until Vcc turns the part on and it senses a low on the input.
The rise should not go above the threshold. since Vcc is very low the drive should be very low so a pull down should hold it low and prevent the rise. To help with this pullups should be on the Oe pins. I am 99% sure you would be OK.
However to be 100% sure you could use a part with power up 3-state. The LVT family has this feature. SN74LVT162244A . This feature keeps the I/o's in try-state until VCC is operational.
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