I've been thinking for a while. Why exactly do we need set up and hold time for flip flops.
I thought it might be because of the input capacitance. But this doesn't make sense when you think of TTL gates.
Also, in some FFs hold time is zero. Why is this.
Setup and hold time is the time wher the clock may not recognize the date. Anything in between setup and hold time is an unstable reagion where the part could read the wrong data. Setup time is the amount of time the data needs to arrive before the clock so the clock will catch it. Sut-up and Hold time can be 0 and may even be stated as a negative number. this can easily happen with TTL parts where the part actually switches at about 1.5V but the measurement for setup and hold is measured at 50% VCC. The part will switch at 1.5V but isn't measured until 2.5V giving the apearance of 0 or a negative number.
Here is an appnot that gives the def of setup and hold times and explains why they may be negative. http://www.ti.com/litv/pdf/szza036b
I think that you may also want to check http://www.ti.com/lit/an/sdya006/sdya006.pdf, which is mentioned in the application note that Chris brought. In few words, setup and hold depend not only of the input capacitance of the FF, but also to the behavior of internal stages in the FF.
Hi!Some stuff about theory: Flip-Flops consist of gates with inputs and a feedback of the output signals (asynchronous time sequential logic). And if one input signal changes the state of the logic changes. During this time, no other input signal is allowed to change to get a well defined behaviour (=> setup and hold time). And some times, both signals may change at the same time (e.g. t_hold=0).Hence, the internal structure (look at schematics of flip flops) and the propagation delay of the internal gates are important.Best regards,Edwin Krasser
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