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  • TI Thinks Resolved

TXB0304: TXB0304, there is serious reflection showed as attached picture when sending 2MHz clock from TXB0304UTR to xilinx XC3S400AN CPLD through 180mm trace

Part Number: TXB0304

There is serious reflection showed as attached picture when sending 2MHz clock from TXB0304UTR to xilinx XC3S400AN CPLD through 180mm trace. Tried below experiment but cannot fix the problem:

  1. Add serial resistor (10,20,30,50,100 ohm) close to TXB0304
  2. Add 10pF+100pF+47pF capacitors near TXB0304 VCC
  3. Add 10pF,100pF,47pF parallel capacitor between CLK to GND close to CPLD

In the figure, blue wave is the input signal and green wave is the output signal.

figure a,  serial resistor vlaue=0Ω

 figure b,  serial resistor vlaue=50Ω

 figure c,  serial resistor vlaue=150Ω

 figure d,  serial resistor not Weld

  • Hi Jian Geng,

    It seems from the other 3 scopeshots that the device is not able to go low down to zero. The output signal is non-monotonic at the falling edge, causing the oneshot internal to the TXB to trigger causing the input to trigger.
    why are these output signals not going down zero?

    It seems like the last scope shot has clean signals as compared to the other 3. what do you mean by serial resistor not weld?
    when you mention having the series resistor close to TXB, is it at the output of the device or the input?
    I would not advise the cap on the output. This will slow the output rise time and hence the prop delay.

    -Thanks,

    Shreyas

    Watch the Introduction to AXC Family

    Read the app note on Power Sequencing for the AXC family

    Evaluate the AXC8T245 EVM and watch the translation using the EVM

  • In reply to ShreyasRao:

    I suspected that the reflection caused by 180mm trace would cause the signal to fail to going down zero, so I removed the resistor in order to disconnect the line and remove the reflection.
    In last scope, the signal can going down zero. Can we assume that the reflection affects the signal?
    The series resistor close to TXB, is it at the output of the device.

    serial resistor not Weld=removed the resistor=the pin on pcb is not connected
  • In reply to jian geng:

    Hi Jian,

    The Xilinx CPLD has internal pullup pulldown resistors as shown here below. This is causing the low level to not reach zero level.

    If there is a way to disable the pullup resistors, it will help the TXB low level go down to zero. The unwanted triggering on the input will also be eliminated due to the smaller voltage level of the signal during low cycle.

    Let me know if this can be done.

    -Thanks,

    Shreyas

    Watch the Introduction to AXC Family

    Read the app note on Power Sequencing for the AXC family

    Evaluate the AXC8T245 EVM and watch the translation using the EVM

  • In reply to ShreyasRao:

    TXB0104 with 16k pullup

     

    TXB0104 without pullup and ~50pF cap loading.

    The slow rising edge is due to the 180mm cable on the output. having larger series resistance will cause to slow down the rise time due to low pass filter. 

    -Thanks,

    Shreyas

    Watch the Introduction to AXC Family

    Read the app note on Power Sequencing for the AXC family

    Evaluate the AXC8T245 EVM and watch the translation using the EVM

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