We are planning to use a 74LVC244 to convert the output of an Avago HCPL5201 opto-coupler output to 3.3V logic levels prior to connection to an FPGA.
The output of the HCPL 5201 goes from 0.5V (logic low) to 3.1V (logic High) with a Vcc of 5V. The rise time is listed as 45 nsec typical or 17.3 ns/volt.
The input transition limit on the LVC244 is 10ns/volt.
By presenting a slightly slower than recommended signal to the LVC input, I assume we may get output glitches during the transition. That we can handle in the FPGA, since we are filtering this signal anyway.
However, we just wanted to make sure we would not cause damage to the LVC input by inducing oscillations/etc.
Do you believe we would damage the LVC244 input?
The LVC244 should not operate at 5V Vcc . I would recoment the SN74LV244AT instead. It can operate at with 5V Vcc. It also has TTL inputs which will put the 3.1V input in spec and rise and fall limits are slower which puts them in spec.
Clarification from the customer:
Sorry for the confusion – the 74LVC244 is operating at a Vcc of 3.3V, while the optocoupler has a Vcc of 5V. The LVC244 is translating the opto 5V logic levels to the FPGA 3.3V levels. The question still stands concerning the input slew rate described below.
More than likely you would not even see any glitches and if you did it would not damage the part but you would still be out of the datasheet limits and it would not be guarranteed. The SN74LV244A would still be a better way to go to keep everything in spec.
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