Hello,
Bus-Switch Application: Save bidirectional FPGA I/O pins from too high or too low negative voltages coming from the I/O interface.
The Digital Bus Switch Decision Tree in the Digital Bus Switch Selection Guide claims that all listed bus-switch families will clamp undershoots at -0.5V when the switch is on. Is this really true? I thouhgt only the CBTS family has such a feature? Or will the CBTS family already start clamping at -0.3V and all others at -0.5V?
Mind: I don't care about undershoot things when the switch is Off. In the application, the switch will always be On. Thanks