Hello,
In my project, I have to delay an input of OR gate for 0.5msec.
Currently, a low pass filter with about 500us time constant is attahced at an input of OR gate IC(SN74AHC32QPWRQ1). An input of the low pass filtter is connected with an output of an AND gate IC. In other words, 500us time constant low pass fitler is connected between AND gate output and OR gate input.
My worry is a large time constant of the low pass filter. in the datasheet of SN74AHC32QPWRQ1, input transition rise or fall time is maximum 20ns/V. But, the transition rise or fall time In my circuit would be very larger than the spec because the time constant of the low pass filter is 500us. But I cannot reduce the time constant because the 500usec delayed input is mandatory.
The 500usec delayed input is not periodical. should I find alternative design to avoid damage of IC and wrong trigger by noise?
If I should, which solution do you recommend? Logic IC with schmitt trigger input? or others?
