In the data sheet SCLS116G, revisied August 2013, on page 3 is the timing diagram titled "Typical shift, load, and inhibit sequence" . This diagram is giving me fits because, from what I can tell it is incorrect, if I, and others I have asked, including TI support people, are reading it correctly. Granted, it has been a while since I have had to read timing diagrams, but I believe I am reading this correctly. The Diagram, as I am interpreting in it indicates the following sequence.
- LOAD the shift register with the 11010101 data from parallel input lines at which point the output, Qh, = H = 1
- Start a shifting operation/sequence at the point the CLK INH goes low and the CLK goes high( same time)
- this is indicated by the dashed line showing the Serial Shift
This is my confusion. The diagram, as I read it, shows the Qh, which is the output of the MSB cell and therefor the output of shift register itself as:
H after CP1, H after CP2, L after CP3, H after CP4, L after CP5, H after CP6, L after CP7, and H after CP8
It almost like It is ignoring the initial clock pulse.
I a pretty sure that it is actually works the following way
H after CP1, L after CP2, H after CP3, L after CP4, H after CP5, L after CP6, H after CP7, value at SER after CP8
Can anyone please clarify this for me.
In an older data sheet, SCHS156A revised May 2000 there is the following statement :
"For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL goes HIGH"
Does the situation discussed in the second sentence have anything to do with this?
Thanks in advance for any clarification.
Jeff