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74HC165 Timing Diagram

In the data sheet SCLS116G, revisied August 2013, on page 3 is the timing diagram titled "Typical shift, load, and inhibit sequence" . This diagram is giving me fits because, from what I can tell it is incorrect, if I, and others I have asked, including TI support people, are reading it correctly. Granted, it has been a while since I have had to read timing diagrams, but I believe I am reading this correctly. The Diagram, as I am interpreting in it indicates the following sequence.

  1. LOAD the shift register with the 11010101 data from parallel input lines at which point the output, Qh, = H = 1
  2. Start a shifting operation/sequence at the point the CLK INH goes low and the CLK goes high( same time)
    1. this is indicated by the dashed line showing the Serial Shift


This is my confusion. The diagram, as I read it, shows the Qh, which is the output of the MSB cell and therefor the output of shift register itself as:

H after CP1, H after CP2, L after CP3, H after CP4, L after CP5, H after CP6, L after CP7, and H after CP8

It almost like It is ignoring the initial clock pulse.

I a pretty sure that it is actually works the following way

H after CP1, L after CP2, H after CP3, L after CP4, H after CP5, L after CP6, H after CP7, value at  SER after CP8

Can anyone please clarify this for me.

In an older data sheet, SCHS156A revised May 2000 there is the following statement :

"For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL goes HIGH"

Does the situation discussed in the second sentence have anything to do with this?

Thanks in advance for any clarification.

Jeff

  • Both H and G have a high loaded so the first two clocks will clock in the high and then F data is low so the 3rd clock it will go low.

  • What do you mean "the first two will clock in" Into what?. The only IN function is the parallel LOAD pulse and it is not associated with the clock. I think you are trying to explain exactly how I am interpreting the diagram, and if so, we are on the same page but that is not how the device actually works from I can tell. My code that has worked for 10+ years, and every single example of code I can find on the net indicate that it actually works it following way. A load latches the input Parallel data and at that point the output Qh represents the MSB that was latched in on the H line. At that point, once the LOAD pin is set HIGH to enter the shift mode, the first rsising edge clock pulse will shift all registers 1 position to the left resulting in Qh being overwritten/replaced by Qg ( a 1 int the diagram)  and so on, with Qa now being the sampled value of SER shortly after the rising edge of the clock pulse. The second clock pulse would result in another shift of all registers 1 position to the left resulting in Qh now being a 0, the F input during the parallel LOAD.

    In contrast, the diagram as I read it shows Qh =1(=H latched input) after the first clock pulse and also a 1 ( the G latched input) after the second pulse, then a 0 (the F latched input) after the 3d clock pulse.... as you stated

    I hope I am making myself clear.

    Thanks

  • On thing, which my be the entire source of my problem, is that I am assuming that the CLK INH transition to LOW along with the 4th CLK transition to HIGH at the same time, as indicated by the second vertical dashed line in the diagram, and that line being indicated at the Serial Shift at the bottom, is the actual first clock pulse of the shift operation resulting in the first bit shift. I also assume this because the diagram adds the H value indication to the output line just after this assumed first pulse while they do not show the value during the Inhibit phase.

    If in fact, the first clock pulse to cause a shift is not actually at this position, but the next one ( the 5th), then that would answer all my questions

    Is that where I have gone astray?