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LSF0108 datasheet figure reference

Per Magnusson
Intellectual 500 points
Other Parts Discussed in Thread: LSF0108

In the third paragraph of section 10.2.1.2.1 of the datasheet for LSF0108, (revised October 2014), a reference is made to the signals A3, B4, Ch1/2 and MDIO of Figure 6. Figure 6 contains no such signals however and there are no other figures that appear to be good fits either. The figure in section 10.2.3 seems slightly more relevant, but nothing is labeled Ch1 or "processor".

I think some cleaning up is necessary.

Also, a general comment on the datasheet is the it is quite hard to understand how the device operates based on the datasheet since important internal details are left out and the explanations are confusing. It is much more instructive to read SDLU003 or SCEA035A.

Per

  • 0
    TI__Genius 9860 points

    Hi Per,

    Thank you for pointing this out. We've been rewriting lots of datasheets lately, so we will look into editing the graphics here.

    If you have anything specifc you'd like to see that SDLU003 or SCEA035A are doing well, please let us know and we will work on making those changes.

    Regrds,

    Ryan

  • 0 in reply to C. Ryan Land
    Intellectual 500 points

    What I miss in the DS and find useful in the other documentation is the schematics of the internals, namely that there are NMOS pass transistors between inputs and outputs and how the Vref_A, Vref_B and EN pins are connected. The fact that Vref_A is the source of a transistor, that Vref_B is the drain and that EN is the gate is quite important and makes the requirement to connect EN to Vref_B and both of them via a resistor to some higher voltage understandable.

    A further suggestion is to rename Vref_A, Vref_B and maybe EN. It is easy to start out by thinking that Vref_A should be the voltage on the A side of the translator and Vref_B should be the voltage on the B side, when in fact Vref_A is the voltage of the lower voltage side of any channel (regardless if it is A or B for any specific channel) and Vref_B and EN are really bias pins.

    I suggest that Vref_A is renamed Vref_lo (since it has nothing specific to do with the A side) and that Vref_B is renamed Bias_D (for drain) and EN is renamed Bias_G (for gate).

    Another thing I was confused about for a while was the requirement of at least 0.8 V (preferably 1V) difference in the signal levels on the two sides. As I understand it now that I have read the other documentation, there is a requirement that the voltage on the high side of the bias resistor to Vref_B/EN shall be at least 0.8 V above Vref_A, but the actual signal levels that the chip translates between can have a smaller difference. So e.g. translating from 1.5 to 1.8 V works fine as long as the bias voltage on top of the resistor is above 2.5 V (and proper pull-ups to 1.8V are used).

    I found this DS to be unusually confusing and hope that you will improve it.


    Per