My system involves LVCMOS2.5 signals and LVDS signals connecting from my FPGA out to the "world" through an LSF0108.
Vref_A = 2.5V and Vref_B = 5V.
I don't want to use pullup resistors on the "world" side, because I want to present high impedance if I disable the translator. I don't need up translation as long as the FPGA outputs will just propagate through to the "world" with minor reduction due to switch resistance. I'm really using the translator to protect my FPGA from excessive high levels on its inputs if a signal from the "world" is 4 or 5 volts for example.
Will this arrangement work properly for LVCMOS2.5 and LVDS signals as outputs or inputs? Each signal line will be an input or output, not bidirectional.
I assume that when enabled, each channel is on unless something such as a pullup pulls the B side voltage higher than the Vref_A voltage. If the B side signal is 4V, then the A side will be about equal to Vref_A (2.5V in my system), with very little current flowing through the channel (assuming the A side is a high impedance FPGA input).
I also assume that a LVDS signal pair will cause the two signal channels to be on because both signals will always be lower than both Vref_A and Vref_B. Thus I assume LVDS signals will work.
Is there anything wrong with my assumptions about this part? Will it work in the system I've described?
Thanks,
Ken