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74LVC2G241DCURE4 maximum frequency

Hello, I need to have two 50MHz clocks in synch but they have to be enabled at different power state on our platform design. I didn't find the output to output maximum skew for the 74LVC2G241 and want to verify if it will be efficient at 50MHz (3.3V) if used as a clk buffer. The scyt129e.pdf (little logic guide) mention that the LVC familly works for 250MHz at 5V but we need to power it at 3.3V. If this part is not suitable for our need, could you suggest an other dual clk buffer (lowest cost). The estimated EAU is arround 4000.