SPI Output Expander using TPIC6C595 and 74xx595 shift registers.

Michael,

I need to understand some more things about your design. Is there a specific design parameter that requires you have a minimum propagation delay and hold time? What is your end application? Could you please attach a block diagram or or schematic of your design?

Minimum propagation delay is not a specified parameter in our datasheets because it is not helpful in design. Parts will have different propagation delays due to variations in the manufacturing process, but we guarantee that the propagation delay will be lower than the maximum. As for hold time, it looks like we only specify minimum hold time.

James

James,

Thanks for your reply.  Please see similar question in the Logic Forum "SPI Expander using SN74LV595A".  He explains the requirement

for minimum propagation delay and hold time. He also explains how the expander works.

However, he is not intermixing types of devices which is necessary for my project.

I have attached a schematic. Only the SPI_CLOCK and SPI_SDO (data) are important for this discussion.

Michael

595 shift example.pdf

Michael,

Thank you for providing the block diagram and the link to the other forum post. I'll have to ask my group about your design and respond by next week.

James

Michael,

I was told that you could consider the minimum propagation delay to be ~3 ns less than the typical value, but this isn't a TI guaranteed value. Other than using the TPIC6C595 for all of your shift registers, the SN74HC595 is the slowest in our portfolio, so it would be the best match of any of the '595 devices.

James

Michael,

I was doing some work recently with an SN74HC595, and I was reminded of your question. I wanted to post on here in case you were still designing and for the benefit of others.

I was looking closely at the timing diagram for the HC595, and it looks like QG is passed to QH' on the negative edge of the clock pulse. It only shows this in the timing diagram, but it isn't otherwise mentioned in the datasheet. I believe this would give you the time delay you need to chain these shift registers together for your application.

James,

I don't think that is correct. If you look at the logic diagram, registers C1 and C2 (7X) are doing the shifting. The rising edge of the shift clock (SRCLK) moves the data from the input (SER) to the output (QH'). The timing diagram also shows the rising edge of SRCLK coincident with the rising edge of QH'. Registers C3 (8X), are used to latch the shift register outputs (via RCLK) and provide outputs QA - QH . However, for this discussion, registers C3, RCLK, and outputs QA-QH are of no interest.

Say you need a 16 bit port expander. You take two of these devices and connect QH' from the first to SER of the second and common the clocks. Serial data output from the micro is connected to SER of the first device. Lets say that we have clocked a full byte of data into the first device and that the next rising edge of the clock will move the first bit into the second device. Lets say the data looks like
00000001. QH' is high, the next rising edge of the clock will bring QH' low. Now SRCLK rises. QH' of the first device will go from high to low.
However, before QH' goes low, the second device must clock in the high on QH'. That is the issue. If the output of the first device changes faster than the required hold time on the second device -- the wrong data is latched into the second device.

Michael,
Thanks for pointing that out. I see now that I was looking at the wrong clock signal. I hope your design is going well. Have you gotten a chance to test it?