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Suggested Logic Buffer for driving TTL 50 ohm load

Other Parts Discussed in Thread: SN74LVC1G97, SN74LVC2G132, LSF0102, SN74LVC1G17-Q1

I have a 20MHz Reference Clock application which has 1.8V output from LVCMOS FPGA I/O and requires conversion to TTL level output.  TTL level is driving into a 50 ohm coax load so I am assuming a 50 ohm source impedance which would yield approx. 2.5V at 50 ohm load end of cable which still meets TTL 2-5V VIH level.  I was thinking about possibly using SN74LVC2T35 or 2 SN74LVC1G97 or SN74LVC2G132 with gates connected in parallel to yield higher drive current required to drive 50 ohm load.  Would you recommend one of these options and/or could you make a recommendation.  I also have a 20MHz Reference Clock input application which would be 5V TTL in (possibly into 50 ohm load) and converted to 1.8V LVCMOS to drive FPGA I/O.  

Thanks,

James

  • Hi James ,

    I understand that the requirement is for translation of 2.5V input to 5V TTL level and there is also requirement for 5V TTL output down converted 1.8V CMOS for FPGA .  how about the LV1T and LSF family of devices  ?

    http://www.ti.com/lit/ds/symlink/sn74lv1t125.pdf - This has 8ma of output drive .

    http://www.ti.com/lit/ds/symlink/lsf0102.pdf - This has max 64ma output drive .

    The power consumption will be usually higher since the application has inputs around the Vcc/2 range.

    Hope this helps , let us know if you have other concerns to address .

    -Thanks

  • Shreyas,

    The 74lv1t125 does not appear to level translate from 1.8V to 5V from a 5V supply or from 5V to 1.8V Also, the drive current of 8mA is not adequate to drive a 50 ohm load. Also, I do not believe the lsf0102 level translation switch could drive a 50 ohm load. My suggestion was to have outputs for one of the dual logic gates mentioned above paralleled to increase drive capability assuming propagation delay between inputs of same device is minimal? Is this okay as long as dual gate of same type and logic family? Other thoughts!!!
  • Hi James,

    The LSF family uses passive translation and does not have any internal drive circuitry -- the output current is based on the device driving the LSF's input (for low output) and the size of the pull-up resistor on the output (for high output).  The operation of the LSF is detailed in the app note, "Voltage-Level Translation With the LSF Family."  The maximum channel current through an LSF device is 128 mA, so I think you will be safe with a 5 V output into a 50 ohm load (100 mA).

    As for putting multiple outputs of the SN74LVC2T35 or 2 SN74LVC1G97 or SN74LVC2G132 in parallel for improved current -- this is a legitimate way to increase current handling capability for our parts.  **** DISCLAIMER: Only do this if the inputs and outputs are tied together -- never tie outputs together for different inputs! ****

  • HI Emrys,

    The device that would potentially be driving the LSF family if used would be an FPGA with max 24mA DRIVE capability or 74LVC1G07 which is only capable of 4mA with a 1.8V supply.  What i am currently thinking is to input 1.8V FPGA Ref clk into a 74LVC1G07  with 1.8V supply and connect open drain PU to 5V to drive and dual NAND GATE (with schmitt trigger inputs?) with inputs and outputs tied to together.  Does this look reasonable or would you recommend a different logic family for dual NAND Gate?  I am assuming a series output term of 50 oms with 50 ohm load yielding a required drive requirement of around 50mA not 100mA.  This should still yield a reasonable TTL logic high level.

  • Emrys,

    Regarding disclaimer, would it be okay to tie 2 inputs to 5V supply and other 2 inputs to 5V output of 74LVC1G07 ? Other option would be to drive all 4 inputs of 2 NAND gates from single 74LVC1G07 output?
  • "The device that would potentially be driving the LSF family if used would be an FPGA with max 24mA DRIVE capability or 74LVC1G07 which is only capable of 4mA with a 1.8V supply.  What i am currently thinking is to input 1.8V FPGA Ref clk into a 74LVC1G07  with 1.8V supply and connect open drain PU to 5V to drive and dual NAND GATE (with schmitt trigger inputs?) with inputs and outputs tied to together.  Does this look reasonable or would you recommend a different logic family for dual NAND Gate?  I am assuming a series output term of 50 oms with 50 ohm load yielding a required drive requirement of around 50mA not 100mA.  This should still yield a reasonable TTL logic high level."

    Just to make sure I understand the question -- you are looking for a NAND gate to take a 1.8 V input and output at 5 V, 50 mA?  Would it be possible for you to post a schematic of your intended system?  I find schematics easier to look at personally.

    "Regarding disclaimer, would it be okay to tie 2 inputs to 5V supply and other 2 inputs to 5V output of 74LVC1G07 ? Other option would be to drive all 4 inputs of 2 NAND gates from single 74LVC1G07 output?"

    If you are saying what I think you are saying, it should be fine.  As long as both outputs are controlled by the same input signals you should be fine.

  • On REFCLKIN side, do you have any suggestions on a logic family/gate that will take in TTL input from 2-5V and output 1.8V? Do yo see any problems with using 74LVC1G07 again and connecting Vcc to 1.8V and ext PU to 1.8V. This would allow VIH min level at input of 74LVC1G07 to be as low as 1.2 based on a 1.8V supply since it looks like input signal level can be as high as 5V over entire supply range of 1.8V-5V? Basically I would terminate CLK IN with 50 ohm termination resistor at input of 74LVC1G07. Your thought and suggestions!!!
  • In regards to REFCLKIN, another option I was considering was an SN74LVC1G97...
  • I believe I have decided to use a 74LVC1G17 for REFCLKIN with VCC tied to 1.8V since buffer with Scmitt trigger inputs. With this device I can input 5V signal into input, pin2, and output voltage level would equal VCC which is tied to 1.8V. Please verify!!!
  • James ,

    I had a look into the schematics and I really don't see any issues with it . The LVC1G07 open drain buffer should pull up the voltage to 5V and since you have connected it to the inputs of LVC2G132 derived from the same supply , the output should be 5V of Refclk .

    "On REFCLKIN side, do you have any suggestions on a logic family/gate that will take in TTL input from 2-5V and output 1.8V? Do yo see any problems with using 74LVC1G07 again and connecting Vcc to 1.8V and ext PU to 1.8V."

    You shouldn't have problem with this setup by having 5V input with Vcc at 1.8V going by the abs max ratings as long as the Max is not tied to Vcc. If at all abs max ratings have Vcc+0.5V , it means that there is ESD diode to Vcc in which case you cant have more than 2.3V at the rated clamp current(50ma) before you damage the device .  

    Schmitt trigger inputs will have threshold voltages before the outputs switch states and hence provide good noise margin .If your inputs are not noisy and has fast enough rise time , you can skip using the Schmitt trigger device but it should work nonetheless in your application .

  • Shreyas,

    Thanks for checking. I noticed in some specifications for 74LVC1G17 that max input voltage is actuallly 6.5V not 5.5V. However, I believe in one automotive specification, SN74LVC1G17-Q1, which may not have been updated showed 5.5V. I am assuming 6.5V is actually input/supply maximum not 5.5V for this logic family device? In regards to above comment, what did you mean by 'as long as Max is not tied to Vcc'. I assume you meant having max VCC of 5.5/6.5V? In this circuit, VCC is 1.8V and the expected output source driving this circuit is 5V with 50 ohm output impedance. When connected to 74LVC1G17 the voltage at input of this logic gate is expected to be around 2.5V across 50 ohm ohm load termination at input side. I have a series 100 ohm termination between load termination and input of 74LVC1G17.

    James
  • James ,

    sorry , perhaps I needed to be more clearer on the phrasing . If you look at the abs max ratings in the datasheet ,the input voltage range is from -0.5 to 6.5V which indicates that under normal operating current the part is not damaged as long as your input voltage range is between -0.5V and 6.5V .This is not related to the Vcc of the device is being operated at . So , looking at your case , Vcc is 1.8V and one of your input being 5V the device should perform as expected.
    There are instances , however , where the abs max is specified as min -0.5V to max Vcc+0.5V ,which means that the abs max of your input voltage cannot go higher than Vcc +0.5V which could potentially damage the device under high current conditions .
    Please note that 6.5V is actually the abs max ratings but the recommended ratings are always max at 5.5V for both Automotive and catalog parts .