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Discussion about CD4010BQDRQ1 Chip

Moataz Fouad
Prodigy 230 points
Other Parts Discussed in Thread: CD4010B-Q1, ULN2003B, ULQ2003A-Q1

Hello,

My application is to make hardware in the loop test engineering for automotive ECU's.

I need to make and interface (buffer) from digital command lines on the ECU (with low logic of 0V and high logic of 12V or up to 24V) to an FPGA I/O lines.

I thought about 2 solutions:
-The first is to use the CD4010BQDRQ1 chip to translate the digital signal of (0V and up to 18V) to (0V and 3.3V), this solution is limited in the high logic voltage which is typically up to 24V for automotive applications.
-The second is to use an OPAMP/comparator with an open-collector/drain configuration, this solution is limited in the speed of the comparator which is required to buffer digital signals with frequency uo tp 10MHz and non-equal rise and fall times of the output signal.

To sum up, I need to make a digital buffer with the following specs.:
-Accepts digital logic signals of 0V low level and up to 24V (or more) high level.
-Generate the output digital signals with 0V and 3.3V to be read by an FPGA.
-Accepts logic signals of up to 10MHz frequency.
-Almost equal rise and fall times.

-I would prefer the solution which has lower high-to-low and low-to-high transition times to avoid distortion in duty cycle of digital output signal at high frequencies.

If you have a suggestion, even using non-automotive chips, kindly let me know.


Thanks in advance,
Moataz Youssef.

  • TI__Genius 14485 points

    Moataz,

    As it looks on the data sheet, the CD4010B-Q1 only has test data up to 4 MHz. It may be possible to run it at higher frequencies, but we do not have data on that operation. Also, the specified transition times are 100 ns to 200 ns for 15 V to 5 V translation. These transition times are getting to be significant for 10 MHz frequencies. That being said, you may be able to use this chip, but I would recommend further testing under your design conditions.

    I have a few follow-up questions so I can make a good recommendation.

    • How many I/O lines will you need to translate between 18 V and 3.3 V?
    • Do you need to only translate 18 V to 3.3 V, or will you need translate 3.3 V to 18 V as well?
    • Are you going to design the system with a fixed logic-high voltage at 18 V, or will there be variation between 12 V and 18 V?

  • in reply to James Lockridge19
    TI__Guru 56050 points
    Hi Moataz ,
    In addition to the shortcomings mentioned above ,this device is not capable of tolerating more than 20V abs max on the input or Vcc .Whats the automotive application which requires up to 24V ? As you have mentioned , the desired option would be #1 to convert to 3.3V but again limitation being the 24V where performance is not guaranteed.
    With option 2 , the speed of the operation is limited by the size of the pull up resistor being used and uneven rise and fall times which could be detrimental in violating the timing spec of the input to FPGA .
    There are ULQ2003A-Q1 , ULN2003B , TPL7407 devices which can be considered for high voltage applications . Have you considered these ?
  • in reply to James Lockridge19
    Prodigy 230 points

    Hello James,

    Thanks for your reply.

    Here're replies to your questions:

    1. I have up to 60 I/O lines to translate between 18V (in some cases from 24V) to 3.3V.
    2. I only need to translate from 18V (in some cases from 24V) to 3.3V.
    3. The incoming signal logic will have the digital low voltage of 0V and the digital high voltage ranging from 5V up to 24V; so I just need a typical threshold of 2.5V to distinguish between high and low logics.

  • in reply to ShreyasRao
    Prodigy 230 points
    Hello Shreyas,
    Thanks for your reply.

    Some automotive ECU's should accept a battery voltage of up to 24V; this is called a cold start condition, where you supply an ECU with double the battery voltage for engine cranking in low temperatures, ex. at 0 degrees.

    For option #1.. the limitation is on the supply voltage which is 20V max.
    for option #2 as you said, the limitation will be the pull up resistor which will cause uneven rise and fall times. I think this problem will be also present when using ULQ2003A-Q1 , ULN2003B , TPL7407 chips .. all of them need pull-up resistors.

    I will be very satisfied if I can find a chip like the CD4010B-Q1 with just increased supply voltage.
  • in reply to Moataz Fouad
    TI__Genius 14485 points

    Moataz,
    Unfortunately, it looks like we don't have a single chip solutions for those requirements. My recommendation is to use open-drain comparators with buffers from the AUP, AUC, AVC, ALVC, or LVC families connected to a 3.3-V rail. If you place the buffers immediately after the comparators, you can minimize bus capacitance, which can minimize the rise and fall time of your signal. The reason I chose those families is because they were made for high-speed applications (see Logic Selection Guide: https://www.ti.com/lit/sdyu001)