Good afternoon I am writing this e-mail, referring to a question I have with respect to the flip flop's the CD4013 chip.
Have read the various literatures respeto thereof, wherein the authors disclose that in the initial state when the circuit is connected, has output Q and Q bar in logic levels 0 and 1. Because it is manufactured with technology CMOS, with complementary stop transistors of N channel and the P channel, and theoretically these two types of transistors need a positive voltage and negative on their doors, to create an electric field, and form the conducting channel brought them cutting and causing them to saturation. In this situation, when the flip flop is energized, theoretically all transistors would be on the court, because no signal is applied to the input D. Also analyzing the internal wiring diagram of the chip, provided in the datasheet of you, I realize that the counter configuration and frequency divider in which the entries set and reset are linked to negative polarity, this also does not help in circuit driving because the internal diagram of it, I could see that these entries when grounded, keeps the transistors of the NOR logic gates flip flop cut. From the above, when the chip is powered up in its initial state, how can the Q BAR output assume the logic level 1, if all your transistors are cut, and no sianal was also applied to the input?
Even in the case of counters, where Q BAR output is fed back to the D input, such as prune the flip flop initiate a count, if no semaphore was applied to entry, to have the level logical 1 at the output Q BAR? It would be the clock oscillator signal applied to the pass gates, the charge to create an electric field therein and carrying the driving transistors and therefore have the logic level at the output Q BAR? I am extremely graphic if you can help me clarify me this doubt. Regards Tarcisio Zewe Duarte Country Brazil city Lapa Paran�state]