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As the flip flop 's the CD4013 chip , go to the initial state Q 0 and Q BAR 1 , when the circuit is energized ?

Good afternoon I am writing this e-mail, referring to a question I have with respect to the flip flop's the CD4013 chip.

Have read the various literatures respeto thereof, wherein the authors disclose that in the initial state when the circuit is connected, has output Q and Q bar in logic levels 0 and 1. Because it is manufactured with technology CMOS, with complementary stop transistors of N channel and the P channel, and theoretically these two types of transistors need a positive voltage and negative on their doors, to create an electric field, and form the conducting channel brought them cutting and causing them to saturation. In this situation, when the flip flop is energized, theoretically all transistors would be on the court, because no signal is applied to the input D. Also analyzing the internal wiring diagram of the chip, provided in the datasheet of you, I realize that the counter configuration and frequency divider in which the entries set and reset are linked to negative polarity, this also does not help in circuit driving because the internal diagram of it, I could see that these entries when grounded, keeps the transistors of the NOR logic gates flip flop cut. From the above, when the chip is powered up in its initial state, how can the Q BAR output assume the logic level 1, if all your transistors are cut, and no sianal was also applied to the input?

Even in the case of counters, where Q BAR output is fed back to the D input, such as prune the flip flop initiate a count, if no semaphore was applied to entry, to have the level logical 1 at the output Q BAR? It would be the clock oscillator signal applied to the pass gates, the charge to create an electric field therein and carrying the driving transistors and therefore have the logic level at the output Q BAR? I am extremely graphic if you can help me clarify me this doubt. Regards Tarcisio Zewe Duarte Country Brazil city Lapa Paran�state]

  • Hi Tarcisio ,

    You are right about the initial state for the CMOS circuits . they are undefined until a valid signal is applied .In case of clocked circuits ,the output is indeterminate before valid clock signal comes in . I will attach an app note explaining the same here .

    6646.scha005a_powerup_clockeddevices.pdf

  • Thank you for your reply and help.
    You're right, because the lines of internal positive connections, close to the lines of the gate of n-mos transistors, can induce charges on the same causing them to conduct, aprecendo unexpected resusltados the outputs. But in the case of the CD4013, the clock signal applied to the gates of passage in the initial state, when the circuit is energized, it causes the circuit fails to behave indefinitely due to internal inteperes, and start to produce in output valid signals, such as Q = 0 and Q = 1 BAR, in the case of an initial counter jhonson?
  • Thank you for your reply and help.
    You're right, because the lines of internal positive connections, close to the lines of the gate of n-mos transistors, can induce charges on the same causing them to conduct, aprecendo unexpected resusltados the outputs. But in the case of the CD4013, this problem is solved when the clock signal applied to the gates of passage in the initial state, when the circuit is energized, it causes the circuit fails to behave indefinitely due to internal inteperes, and pass to be output valid signals, such as Q = 0 and Q = 1 BAR, in the case of an initial counter jhonson?
  • The initial state being undefined would not mean they will be in Hi-Z but that the output can be a 0 or 1 depending on the what the input pins signal picks . Since Q and Q\ cant be equal , they output low and high respectively or vice versa .
  • Good afternoon Shreyas Rao, very grateful for your reply, and the article that sent me. So in this case is the electric field of the positive + internal Vcc lines of the integrated circuit, which attracts electrons from the gates of the transistors mosfet's the n-channel, inducing a moment bias in them, and making the drive?


    Other questions regarding the article: The first is with respect to the method of use of the inputs SET and RESET, if the RESET input more accurately, only in an initial shelf when the circuit is energized, should be applied in the same low level , to have the outputs Q = 0 and Q '= 1, then the same must be brought to a logic low level so that the flip-flop can operate normally. I wonder how it's done iss: take the RESET input, or PRESET, to have the Q and Q 'outputs in their respective levels, then levvar these entries to the levels of normal operation by the flip-flops? Circuits that are used to control these entries?


    And another question is nometodo clock delay when several pulses are applied to the same flip flop, as is done to block the exits until it has valid signals?