I wish to parallel 4 gates of the CD74ACT273SM96 and match this quad "super-gate" with another "super-gate" formed by the parallel combination of the remaining 4 gates in the package. If I knew the physical layout of the chip, I could select two groups of 4 that would provide the best matching (in RdsON, delay, rise/fall time) of the two "super-gates". Could you please provide the gross floor plan of the chip so that I can select groups of 4 that are interleaved in the physical layout? I could also use the 74ACT374 or 74ACT574, so information on these would also be helpful.
- Thanks!