CD40107B Open-Drain configuration

Jared Becker

Other Parts Discussed in Thread: CD40107B

Hi Team,

I am using the CD40107B NAND Gate in my application in the following manner:

Can you please help answer the following questions:

1. This is not used in the typical open drain configuration, where the output is pulled-up using a resistor and then applied to a load as follows:

Is it ok that the load is part of the pull-up? What are the risks associated with this implementation?

In my implementation, I can use the FET inside the NAND gate to turn on and off my load, but since my load is part of the pull up I am not sure what consequences could result.

2. In the datasheet, there is a graph that I am struggling to understand:

If the output is "low" as it says in the caption, why is the drain-to-source voltage (Vds) at such large voltages?

I am assuming this graph is referring to the following FET:

In my application, Vss is tied to ground, so a Vds of 5V, 10V, or 15V does not seem like a "low" to me..

Thank you for your help here.

Jared

over 7 years ago

0 Clemens Ladisch over 7 years ago

Guru 243220 points

A pull-up resistor is needed when the output is a signal that must have a defined voltage level even when the open-drain output is off.
In your application, there is no output signal; you're just switching a load.

An output being "low" means that the output is connected to ground through the FET, but you will get a voltage drop over the FET when you are trying to sink too much current. (All FETs behave this way.)

When you're using the output for signalling, you must stay far away from too-large currents, or the output isn't seen by other devices as being low.
When you're using the output for switching a load, you must stay far away from too-large currents, or most of the power will be dissipated in the FET, and it will be fried.

And the typical values are not very useful for designing a circuit; you have to use the guaranteed minimum/maximum values to determine whether your circuit will work.

0 user4766561 over 7 years ago in reply to Clemens Ladisch

Prodigy 170 points

Hello guys,

where is the diode parallel to the motor and maybe also a capacitor(10nF as an example)?

0 Jared Becker over 7 years ago in reply to Clemens Ladisch

TI__Genius 11495 points

Hi Clemens,

Thank you for the details about using the NAND gate to switch a load.

In terms of the output low explanation, I am still not quite clear. Why is the minimum spec'd and not the max? There are negative consequences if too much current flows through the FET, but what are the consequences of having less than the minimum current flow through the FET? Since there are negative consequences if too much current flows through the FET, shouldn't this be spec'd as a max?

Thank you,

Jared

0 Clemens Ladisch over 7 years ago in reply to Jared Becker

Guru 243220 points

When less current flows through the FET, there is a smaller voltage drop.

The sink currents are specified for certain voltage drops. This means that the minimum current is the worst case; e.g., some particularly bad device has such a high output impedance that it already reaches a voltage drop of 0.5 V at a current of 50 mA.

0 Jared Becker over 7 years ago in reply to Clemens Ladisch

TI__Genius 11495 points

Hi Clemens,

Do you mean to say "a voltage drop of 5V at a current of 50mA"? or am I misinterpreting the graph?

That makes for quite a large Rdson - 100 Ohms.

That seems like a really large Rdson...

Thank you,

Jared

0 Clemens Ladisch over 7 years ago in reply to Jared Becker

Guru 243220 points

I am referring to the electrical characteristics tables; at 25 °C, with V_CC = 15 V, and V_O = 0.5 V, you can sink at least 50 mA. That is, worst-case R_DS(on) is 10 Ω.

0 Dennis Eichmann over 7 years ago in reply to user4766561

Guru 74080 points

user4766561 said:
where is the diode parallel to the motor

Jared, if you want to switch an inductive load as shown in your picture, don't forget this statement. A diode antiparallel to the inductor (motor) might be necessary. Switching off an inductive load will cause a sudden voltage spike that might damage the FET. The diode prevents this.

Dennis

0 Jared Becker over 7 years ago in reply to Clemens Ladisch

TI__Genius 11495 points

Ok, but the worst case Rdson according to the table then would still be ~25 Ohms:

0.4V / 0.016A = 25Ohms. That is still a very large Rdson. Am I understanding this correctly?

Best,

Jared

0 Jared Becker over 7 years ago in reply to Dennis Eichmann

TI__Genius 11495 points

Thank you, I have that but just drew a quick diagram in visio. Appreciate you looking out

0 Clemens Ladisch over 7 years ago in reply to Jared Becker

Guru 243220 points

The 16 mA minimum is only for V_DD = 5 V, which reduces the gate-to-source voltage of the output MOSFET.

0 Jared Becker over 7 years ago in reply to Clemens Ladisch

TI__Genius 11495 points

Right, but if I'm using Vdd = 5V then I must follow this spec, resulting in a Rdson = 25 Ohms. Thus, this device has a worst case Rdson of at least 25 Ohms, correct?

0 Clemens Ladisch over 7 years ago in reply to Jared Becker

Guru 243220 points

Yes; if you choose to use V_DD = 5 V, you might get 25 Ω.

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CD40107B Open-Drain configuration