SN74LVC1G123 - The pulse of Q does not appear.

Dice-K

Mastermind 6330 points

Other Parts Discussed in Thread: SN74LVC1G123

Hello,
I have a question about SN74LVC1G123.

When "B-terminal changes from L to H," the output of Q appears.

But when "CLR-terminal changes from L to H", the output of Q does not appear.

Is the behavior of this IC wrong?
It does not work like the Function Table.

Regards,
Dice-K

over 7 years ago

0 ShreyasRao over 7 years ago

TI__Guru 55970 points

Hi Dice-K

It does seem that device is not functioning according to the truth table.
Could you have the B high in steady state before the CLR goes high ?
Are all devices you have behaving similarly or is this limited to single device ?

0 Dice-K over 7 years ago in reply to ShreyasRao

Mastermind 6330 points

Hello Shreyas,
Thank you for your reply.

All devices (15 pieces) behave similarly.

The rising of CLR is 0.2s late behind B.
Is it necessary to increase a delay?

Is it a problem that CLR has a small hazard at the time of B rising.

Best regards,
Dice-K

0 Emrys Maier over 7 years ago in reply to Dice-K

TI__Guru* 96591 points

Hi Dice-K,
Could you grab a scope shot of the inputs + the external capacitor voltage when the error occurs for me? I'm looking into possible causes for this.

0 Dice-K over 7 years ago in reply to Emrys Maier

Mastermind 6330 points

Hello Emrys,
Thank you for your reply.

The phenomenon does not change even if I delay the rising of CLR.

I attach the circuit.

one_pulse_output_circuit.pdf

When I used TC7WH123FU of TOSHIBA, It worked.
toshiba.semicon-storage.com/.../detail.TC7WH123FU.html

Could you teach me check points?

Best regards,
Dice-K

0 Emrys Maier over 7 years ago in reply to Dice-K

TI__Guru* 96591 points

From the scope shots you showed above, it looks like there might be a trigger when B goes high (CLR also has a large spike there). Since CLR immediately goes low again, the output would be suppressed, however the recovery time would still be in effect.

0 Dice-K over 7 years ago in reply to Emrys Maier

Mastermind 6330 points

Hello Emrys,
Thank you for your reply.

The output does not appear even if I change CLR to High and Low in a state of A=Low and B=High several times.
Therefore I do not think that the reason is the rinsing of B or the spikes of CLR.

Are there other causes?
Is there the problem with a circuit?

Best regards,
Dice-K