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SN74LVC1G123: input/output timing diagram question

Part Number: SN74LVC1G123
Other Parts Discussed in Thread: STRIKE, SN74LVC1G06

Hi Team,

customer design the SN74LVC1G123 device for their control circuit as attached, they found sometimes when the B signal(pin2) is in high state however the Q signal(pin5) output is keep high but not like H/L toggle as data sheet input/output timing diagram shown.  Customer thought the problem could be the Rext/Cext(pin7) value setting related, so they want to know what is the voltage threshold level requirement of the Rext/Cext signal and what is the Rext/Cext value setting range to get the Q singal(pin5) go to low?

Your advise and comments for this issus clarify is very appreciated.

Regards,

Arthur

  • Hi Arthur,

    The output is triggered by a rising edge on the B input when A\ is held low and CLR\ is held high. The output will switch back to low when the external capacitor voltage reaches ~63.2% of Vcc.

    If you can share an oscilloscope shot of the A\ B and CLR\ inputs and the Q output together we can try to troubleshoot any issues.  Also, there is a great application note on this device located here that you might find helpful.

  • Hi Emrys,

    one more queston from customer that what is the reason the R/C signal(pin7) is only 2.2v but not reach to 3.3v? Please advise. Thanks.

    Regards,
  • Based on the schematic you have provided, there is no reason for that to happen. Can you provide an oscilloscope shot of the B, R/C, Vcc and Q pins together so we can try to troubleshoot?
  • Hi Emrys,

    Attached is the B, Q, R/C waveform. Note that from customer feedback if they change the R596 resistor value from 470K ohm to 235K ohm, the voltage level is increased from 2.2V to 3.2V. So, customer wnats to know if any restriction of the Rext resistor value? what is the max of the Rext value? Please advise. Thanks.

    Green color for Q terminal.

    Purple color for B terminal.

    Brown color for Rext/Cext.

  • Hi Arthur,

    It appears that the internals of this device may have been damaged.  You should see no more than 0.25uA leakage into the Rext/Cext pin on the device, but based on what you have told me, you are getting between 0.425uA and 2.3uA.  Have you tried swapping to a new device?

  • Hi Emrys,

    You are right, after customer swapped a new device, the problem is gone. However, since the failure rate is quite high which is 9pcs/10000pcs, so customer wants to know the problem root cause. Below are the questions customer wants to check you for answers.

    1. any restriction of the Rext resistor value? what is the max of the Rext value?

    2. how do you calculate to get the 0.425uA and 2.3uA number? How do you know the device was damage that you mentioned on previous replied?

    3. any concerns for the customer circuit?

    Thanks.

    Regards,

    Arthur

  • There is no official limit on the Rext value, however the 0.25μA maximum leakage into the device will create a voltage drop of 0.25V on a 1 MΩ resistor, so I would recommend keeping it smaller than that.

    To calculate the leakage current, I just used ohm's law. I = (VCC - VR/C)/Rext

    The circuit seems fine.  My first guess for damage is usually ESD.  These device do have some intrinsic ESD protection, however it is limited and they should be handled with extreme care during the manufacturing process.

  • Hi Emrys,

    customer feedback that when they adjusted the R597 resistor value from 470k to 100k, the problem got improved, so they want to know if any concerns of changing the Rext to 100k? And why use 100k that help to improve the failure rate?

    On the other hand, since you mentioned the SN74LVC1G123 has limited ESD protection, so customer wants to know if we have p2p device that has strong internal ESD protection feature than SN74LVC1G123?

    Thanks.

    Regards,
    Arthur
  • Hey Arthur,

    I wouldn't expect the resistor change to affect the reliability of the part - perhaps the reduced resistance intrinsicially improves the ESD resistance of the circuit overall?

    I'm afraid we don't have an equivalent with strong internal ESD protection. If any of the traces going into the device are externally accessible (ie likely to take an ESD strike) during operation, I would recommend adding external ESD protection to those traces (which is good practice for _all_ external connectors).
  • Hi Emrys,

    Attached is customer latest schematic, they are asked if BU can help to confirm the R/C value of this schematic design whether meets the SN74LVC1G123 device spec requirement or not? Your prompt response and comments for this requested is very appreciated.

    Regards,

    Arthur

    fwb-2200b10_0807a.pdf

  • Since the B-input to the SN74LVC1G123 uses a Schmitt-trigger architecture, I believe they could eliminate this circuit entirely and replace it with a simple RC connected from +3.3VDual to ground.  The resistor/capacitor size would determine the delay, and the cost savings would be significant.

    If they feel that this circuit is definitely required, I might recommend replacing it with an RC + Schmitt-trigger or an SN74LVC1G123 -- both of which would be far more cost effective than the current solution and provide the same function (unluess there is some part of the function that I don't understand).

    While it is not entirely necessary, I would recommend adding a ~50 Ω resistor between C124 and the R/C voltage node (indicated as Ri above).  This resistor is intended to limit current into the SN74LVC1G123 during the discharge cycle and power-off. Large capacitors can hold a significant amount of charge and can cause undue stress to the internal discharge circuitry.

    The added resistance will cause a slight change in timing, but with a 470kΩ timing resistor, the change will be negligible.

    I noted one other minor possible change as well:

    While a cheap solution, this BJT inverter is not very power or space efficient -- I would recommend at least looking at using an SN74LVC1G06 (open-drain inverter) instead.