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CD74HC74: A giant leap in synchronous logic design with 74 /-000 devices

Serge Mathieu
Prodigy 195 points
Part Number: CD74HC74

Hi every one,

I have been designing complex digital ASICs for the last 20 years. I developed design techniques and devices that could be used at advantage in 74 / 4000 like devices, allowing for

FULLY SYNCHRONOUS DESIGNS (FSD) using these devices. FSD greatly simplify the design process, timing analysis, while increasing robustness and reliability. 

FSDs are glitch-immune. These technique and devices may be also be applied to FPGA, ASICS, full custom ICs, etc.

My suggestion in this forum is that manufacturers add a few new devices to the 74 / 4000 families, to allow them to build FULLY SYNCHRONOUS SYSTEMS. 

Since I did not find a way to paste circuit drawings in this post, I post a link to a short pdf document. 

https://www.dropbox.com/s/rvttrzwt48gmki5/SyncDesign2.pdf?dl=0

For those designing with 74/4000 devices, (which are not fully synchronous devices) and even for those designing with FPGAs or ASICs, reading this document could change the way you design systems. 

smathieu13@hotmail.com

 

  • 0
    TI__Guru* 96591 points
    Hi Serge,
    Thanks for the post.
  • 0 in reply to Emrys Maier
    Prodigy 195 points
    Thanks for thanking me for the post. However, more could be done.

    I have clarified the above document in a second post referring a clarified document. I believe that Enabled and Synchronous devices are the answer for simplified and more reliable logic designs.

    Consequently, TI should market a set of Synchronous and Enabled logic devices; these powerful devices are missing in TI's products.

    I would like the second document referred below be analysed by the logic products engineering staff. These techniques and devices allowed me to design very complex digital ASICS, like this one.
    www.dropbox.com/.../AC-PLM-1_User_Manual.pdf

    My conviction is that TI and the whole discrete logic community would benefit from the concepts and devices described.

    Please, refer this document to a higher level in TI's hierarchy, up to the engineering staff, for analysis and back comments.
    Thanks.
    www.dropbox.com/.../SyncDesign2.pdf
  • 0 in reply to Emrys Maier
    Prodigy 195 points

    Here is an example of the power and ease of use of enabled devices: (An image is worth a thousand words: the VHDL code is 22 pages long... ) This is a 8 bit by 8 bit shift and add sequential multiplier. (Not a real design: just to show the enabled principle. Buffers omitted, clock and async. reset not shown, etc. It is not necessary to draw the clock: there is a single system clock for the whole design.) See FSD rules. Start is an Event: a one-clock-wide synchronous pulse.Should paths delay of the adder be longer than the clock delay, pulse the ST1 signal. 8 clocks or less are required to make the multiplication. A 16 bit divided by 8 bit is also simply designed with the shift and substract method.The same for first, second order, etc. low pass, band pass, high pass filters, synchronous FIFOs, successive approx. registers, etc. 
    www.dropbox.com/.../8Mply.jpg