Hi every one,
I have been designing complex digital ASICs for the last 20 years. I developed design techniques and devices that could be used at advantage in 74 / 4000 like devices, allowing for
FULLY SYNCHRONOUS ENABLED DESIGNS using these devices. Synchronous enabled designs greatly simplify the design process, timing analysis, while increasing robustness and reliability.
These designs are glitch-immune. These technique and devices may be also be applied to FPGA, ASICS, full custom ICs, etc. They facilitate migration from discrete devices to FPGAs, Asics, full custom.
My suggestion in this forum is that Texas Instruments adds a few new devices to the 74 / 4000 families, to allow them to build SYNCHRONOUS ENABLED SYSTEMS.
Since I did not find a way to paste schematics drawings in this post, I post a link to a short pdf document.
For those designing with 74/4000 devices, (which are not fully synchronous devices) and even for those designing with FPGAs or ASICs, reading this document could change the way you design systems.
Enjoy!
smathieu13@hotmail.com
