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SN74HC573AQDWRQ1 The output (Q) will have an indefinite output

Other Parts Discussed in Thread: SN74HC573

In the actual application, we find that the locked output (Q) will have the output of the indefinite state. At present, we suspect that it is caused by the upper current sequence, please help to analyze.

1. What is the correct electrical time sequence of this chip?OE, VCC and D

2. If not according to the current sequence operation, the output transient is abnormal.

3. What is the situation and how to avoid the switch of electric power in OE and VCC?

  • What do you mean with "locked"? LE low, or OE high?

    What transient? Did you intend to attach an oscilloscope screen shot?

    As mentioned in the datasheet, OE should be tied to VCC with a pull-up resistor. Did you do this?

  • Hi,
    The SN74HC573 is a latch, which means that it does not have a defined output state at startup. It could start in the 'high' or 'low' state.

    The only way to be certain of the output state is to force the output into a high impedance state with 'OE\' and then clock in data with LE and D before releasing 'OE\'