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24-bit Bidirectional Buffer

Raja Ashutosh Kedia
Intellectual 430 points
Other Parts Discussed in Thread: TXS0108E

Hi,

We are looking for a 24-bit bidirectional buffer (3.3V signals) with minimum propagation delay and skew. Can you please suggest us a suitable device?

Regards,

Raja

  • 0
    TI__Guru* 96591 points

    Hi Raja,

    It sounds like you're trying to find a transceiver (direction controlled bidirectional buffer). The absolute fastest devices we have are in the SN74AUC family, however they have a maximum voltage of 2.7V, so this application won't be able to use those.

    Your best bet will be using our parametric search tool.  I narrowed down the list here:

    From my quick search, the SN74ALB16245 is probably the best fit, but I'll let you take a look and decide for yourself.

  • 0 in reply to Emrys Maier
    Intellectual 430 points
    Hi Maier,

    Thanks for the response.

    We need the Buffer to increase the drive strength on GPMC interface. As the data lines are bidirectional, we need a bidirectional buffer. I found a TXS0108E device, which can operate without need of DIR signal. Can you please confirm, if we can use this device for GPMC interface?

    We are planning to add the GPMC data and control lines through 3 such TXS0108E buffers, while the address lines are connected directly without any buffer. Hence, the address lines will have less delay than the control/data lines. We feel that as the GPMC address signals are expected to be valid before any Control signals, this should be fine. Also, there is a skew of 1ns for TXS0108E device. Can you please suggest the maximum frequency we can safely operate with this skew for GPMC interface. Please let us know if you see any other issues with this scheme as well.

    Regards
    Raja
  • 0 in reply to Raja Ashutosh Kedia
    TI__Guru* 96591 points
    Hi Raja,
    The TXS0108E isn't a buffer and won't add drive strength to a communication line. It is specifically designed for voltage level translation.

    I'm afraid I am not familiar with the GPMC interface and Google isn't being very helpful. Can you give me details regarding the operation of GPMC in your system?

    Are all 24 bits going the same direction/switching at the same time?

    Is the data direction unpredictable - ie the data lines switch from A->B to B->A without any warning, or is there a read/write bit used that controls the data direction?

    What's the max data rate?

    What are the load conditions?

    The more information
  • 0 in reply to Emrys Maier
    Intellectual 430 points

    Hi,

    Thanks for the quick response.

    As TXS0108E doesn't provide buffer operation, we are planning to use 3 SN74ALB16245 devices and connect all GPMC Address/Control/Clock/Data lines through this buffer.

    I looked at the SN74ALB16245 datasheet and I have few queries to assess timing requirements for GPMC interface.

    1. What is the delay from DIR pin to A or B ports? The datasheet mentions about OE to A/B delay, is it also applicable for DIR pin?

    2. What is the skew across these channels (maximum difference in tpd for two channels)? I see tpd range from 0.6-2ns. Does it mean the skew is 1.4ns or does it mean that all channels will be delayed by same value and that value may range between 0.6-2ns and hence skew would be zero?

    Regards

    Raja

  • 0 in reply to Raja Ashutosh Kedia
    TI__Guru* 96591 points

    Hi Raja,

    The delay for DIR is the same as that for OE - note from the logic diagram on page 3 of the datasheet that they have identical propagation paths.

    The skew for logic devices is ≤ 1 ns (assuming equal loads) unless otherwise stated in the datasheet.

  • 0 in reply to Emrys Maier
    Intellectual 430 points
    Hi,

    Can I leave the unused IO pins as floating? I do not see any recommendation in datasheet.

    If not, do I need to provide external pull-up/down resistors on the used IO lines in order to protect the buffer when they are not driven by the Processor, as I do not see any bus hold circuit in the device. Or will the internal PU/PD of the Processor would be sufficient for the same? Can you please suggest on the same?

    Regards
    Raja
  • 0 in reply to Raja Ashutosh Kedia
    TI__Guru* 96591 points
    Since this is a BiCMOS device, leaving the inputs floating will likely cause problems. Since the leakage current is lower for the inputs = Vcc, I would recommend tying them directly to Vcc (no resistors are required). Note from the Electrical Characteristics table that the inputs will sink 0.6mA if connected directly to Vcc, but 1.0mA if connected directly to 0V.