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SN74LVC257A: Voltage at the I/O pins when device is not powered

Jerry%20Leung
Intellectual 905 points
Part Number: SN74LVC257A
Other Parts Discussed in Thread: SN54LVC257A, SN74CB3Q16244,

Hi team,

Just want to double check and confirm for a customer if there would be any issue (voltage limit violations) if there is voltage at the I/O pins when the device is not powered (VCC = 0V)?

Same question as my other E2E post here, but want to verify with the SN54LVC257A as I don't see the particular test condition in the datasheet.

Thanks for the help and confirmation,

Jerry

  • 0
    TI__Guru* 96591 points

    Hi Jerry,

    First, are you really planning on using the SN54LVC257A together with an SN74CB3Q16244?  I find it odd that you would match a military grade and civilian part, so I'm going to assume that was a typo. It also seems odd to me that you're using one active (gate based) mux and one passive (switch based) mux.  Is that intentional?

    Part of this answer is one of the most frequently asked questions for standard logic devices.  We have an answer posted here that you might like to read.

    That is specifically in reference to the input voltage -- since you asked about the outputs as well, I will have to add to it.

    The SN74LVC257A datasheet lists the absolute maximum voltage on the input as -0.5V to 6.5V, which means there is no positive clamp diode and it is safe to apply a voltage to it.  The listed maximum on the output is -0.5V to Vcc + 0.5V.  This could be problematic for your application.  If you apply a voltage to the output, the output parasitic diode in the pFET will turn on and allow current to back-flow into the Vcc of the device and turn it (and anything on the bus) on.

    I did not find a similar part in our portfolio with the Ioff feature.