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SN74LVC2T45: About power up sequence

Toshiyuki
Mastermind 7075 points
Part Number: SN74LVC2T45
Other Parts Discussed in Thread: SN74AXC1T45

Hi,

Please let me know about power up sequence for SN74LVC2T45 under the following conditions. Does VCCA need to power up before VCCB, or vice versa ?

VCCA=3.3V

VCCB=1.8V

DIR=0V

Best Regards,

Toshiyuki

  • 0
    TI__Guru 56100 points
    Toshiyuki san,

    what is the status of the IO ports?
    Assuming the IO ports are grounded (or with low pulldown), the Vcca ramping after Vccb OR Vcca ramping along with Vccb is advised.
  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi Shreyas san,

    Thank you for the reply. Yes, IO ports are grounded. If DIR is with pullup, do we need to ramp Vccb after Vcca ? Please tell me the reason about the sequence.

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points
    Toshiyuki San,

    The power sequencing is only a recommendation from TI not a strict guideline for operation. There will be no damage to the device or reliability concerns if implemented in any other way or sequence.
    The overall system functioning and reliability must be the priority. I recommend IO ports grounded as the floating nodes can create unknown voltage levels which may spike while the power is still ramping and which may cause unintentional system behaviour.
  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi ShreyasRao san,

    Thank you for your answer. Our customer's system isn't acceptable for any spikes while the power is still ramping. If the Vcca ramps after Vccb, can we prevent the spikes?

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points
    Toshiyaki,

    Yes, I understand the concern about the customer system not to have spikes ( which is always desired).
    There will be no spikes with Vcca ramping after Vccb, with IOs grounded.
  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi ShreyasRao san,

    If DIR is with pull-up, can we prevent the spikes by ramping Vcca after Vccb?

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    Mastermind 7075 points

    I'm still expecting your response regarding power up sequence. Please let me know if there is a method of avoiding spikes 

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points

    Toshiyuki san,

    As I have mentioned earlier, there will be no glitches when IO ports are grounded, with Vcca or Vccb ramping up first.
    If you have any concerns, please let me know.

  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi,

    Customer conducted experiments about power up sequence. Unfortunately, the spikes occurred when ramping Vcca after Vccb with DIR=high. I need to explain the mechanism of the spikes. Would you tell me more information? 

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points

    Toshiyuki san,

    I am unable to explain the mechanism of the spikes as these are internal analog design files without access to applications.

    I want to know each existing condition of the device pins(Vcca, Vccb, IO pins, control pins) while this happens.

  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi ShreyasRao san,

    I've already sent you a private message with customer's results. Please review it.

    Best Regards,

    Toshiyuki

  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi ShreyasRao -san,

    For DIR=H, will there be no glitches when IO ports are grounded with VCCA ramping up first?

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points
    Toshiyuki san,

    I cannot explain the internal design or the reason why the spikes are being seen, however, I can assure you that the reliability of the device will be intact when power sequencing is done with either Vcca is ramped up first or Vccb is ramped up first or if both are ramped together.

    I would advise the customer to have power sequencing in such way that there are no glitches seen during ramp up or ramp down ; which will mitigate any undesired system level operation.

    I would also at this point recommend the customer to consider using the SN74AXC1T45 device we recently released which guarantees operation with any power sequencing combinations.
    I have also an app note link here below for reference which specifically talks about this device power up / down sequencing
    www.ti.com/.../scea058.pdf
  • 0 in reply to ShreyasRao
    Mastermind 7075 points

    Hi,

    Thank you for your reply. unfortunately, the spike problem is causing in customer's test process for mass production.So that, they need to resolve by altering the current software. Judging from the evaluation results that I sent you in a private message, for DIR=H, will there be no glitches when IO ports are grounded with VCCA ramping up first?

    Best Regards,

    Toshiyuki

  • 0 in reply to Toshiyuki
    TI__Guru 56100 points
    Hi Toshiyuki san,

    Based on the experiments done so far, i believe that the glitches are occuring when Vcca ramping after Vccb and when the DIR is high with IO ports at gnd.
    I conclude that the Vcca ramping before Vccb will not cause glitches in the system while all the other pins held in their same state as before.(IO ports gnd and DIR high)