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SN74HC163: MSB toggles after 2048 count reset

Part Number: SN74HC163

I am using three of these counters clocked from an encoder that provides 2048 pulses per revolution. Even though the CLR pulse occurs at the right time the twelfth bit (MSB) continues to count without resetting. In the past the twelfth bit stayed low. Now it stays high for one clock pulse extra and then resets with the rest of the bits. 



  • Hi John,

    Welcome to e2e. I have notified the engineer to take a look into this.
    It would helpful for us if you can zoom into the scopeshot to the rising and falling edges as well as providing a schematic for the application.
  • I am including a blowup of the signal capture I sent originally. Monday I go back to the lab and can do a better job of capturing the leading and trailing edges of the Q11 and Q12 signals you asked for rather than just blowing up the original. I am also including the schematic.

  • Here is a more careful measurement of the leading and trailing edges of the last two counter stages. Thanks, Jack

    Q11 Leading Edge

    Q11 Trailing Edge

    Q12 Leading Edge

    Q12 Trailing Edge

  • Hi John,

    Thanks for the schematic and the zoomed in scope shots. I need to see the CLR pulse included in the scope shot so I can see the issue you are seeing. Also, have you tried doing an A-B-A swap? It'd be a good idea to do this since you said this exact circuit has worked in the past just to see if it isn't an issue with the device.
  • Dylan,

    Below are the captures for CLR' and Q11 plus CLR' and Q12. I captured these earlier when I was trying to figure out what was happening. Hopefully this is what you need. I am a volunteer at the Office of Archaeological Studies, New Mexico living in Albuquerque. I go up to OAS about twice a week so it may take a day or two to get any data you need.

    I am not sure what you meant by the A-B-A swap. Are you referring to the clock pulses as the encoder outputs out A and B pules that are quadrature pulses? I have generally always used the A Clk so this may not be an issue. However, I can try it next trip and let you know.

    Thanks for the consult.

    Jack

    Below are the CLK' and Q pulses:

    CLR' and Q11


    CLK' and Q12


  • Should have been CLR' throughout. I said incorrectly CLK' in some places. 

  • Hi John,

    By A-B-A swap I mean swapping a known working device with the device that isn't working to see if that fixes the problem. That indicates there is an issue with that device. However, from both recent scope shots I see the output go low on CLR. Is this not what you want?

    Also no worries about the time it takes to get data, I'm tracking this thread so whenever you reply I'll see.
  • Dylan,

    Thanks. The IC is soldered in so swapping is hard but doable. The problem however, is that there are 2048 pulses produced by the encoder for each revolution of the shaft. I am using three 4-bit counters to count the pulses so I can generate a sync pulse for the frequency demodulator. Q5 is the sync pulse used. However, it seems the entire cascade of counters should work properly to ensure Q5 and the entire chain is synchronous. This means the last counter gets to 1110 and then is reset to 0000 in sync with all the other counters. So the counters show: 1111 1111 1110 (MSB on right). At the next pulse CLR' resets the counter to 0000 0000 0000. Instead the counters show 1111 1111 1111 at the 2048th bit (a count of 2047) plus one instead of all zeroes. This means Q12 is not being reset when it should be even though the CR' to that counter is present.

    Hopefully I have made this clear enough for you to diagnose the problem. 

    Jack

  • Hi Jack,

    The A-B-A swap will determine if one of the counters isn't working properly. As you said "In the past the twelfth bit stayed low" indicating this a new occurrence. If the circuit wasn't modified from that point than this could be a possibility. However, I've gotten two scope shots with 2 different outputs showing them go low with the CLR going low which seems like it is working. Another thing, you say 1111 1111 1110 (MSB on right) turns into 1111 1111 1111 on the next clk cycle. That shouldn't be the case unless you meant LSB on the right.
  • Hi Dylan,

    Yes, you're right, I got MSB/LSB backwards. I am going up to the lab Monday and will bring the circuit board back to replace the 3rd counter. I think you are right in that the only way to know is to change it out. If I am only using Q5, the fifth stage as a sync pulse the following stages, Q 6-12 should have no effect on whether Q5 is in sync (assuming all previous stages are working, After I change the IC I'll let you know where things stand and if necessary move on from there.

    Thanks for your help.

    Jack

  • Hi Jack,

    Were you able to do the swap? I can't really help you debug the system as a whole. I'm mainly focused on making sure the counter is operating like its supposed to. In this case, if it isn't outputting Low when it is cleared then there is something wrong. The scope shots provided have shown proper operation so far though.
  • Dylan, 

    I thought I had spare ICs but didn't so ordered and they arrive today. Will install this weekend and return to the lab Tuesday to test. I realize you are not looking at the whole system. The trigger required by the rest of the system needs to be LVCMOS (3.3 V) levels and by my reading these counters meet that requirement. The scope shots I sent hopefully show the correct levels and rise/fall times. However, my concern is not that the last stage, Q12, doesn't go low, but that it keeps counting when it should be reset and not count at all since one full cycle is 2048 pulses per revolution. At one time Q12 would always stay low as the full series of pulses were not enough to require a count beyond Q11. So as in one of the captures you can see Q12 count when it shouldn't. If the fault is the last IC the counters should return to the correct operation with Q12 never going high. 

  • Hey John,
    I just wanted to let you know that Dylan is going to be out of office until late next week.

    I can help if necessary until Dylan gets back.
  • The last stage Q12 toggles still even though it should not as the counters reset after 2048 pulses. Here is a scope capture:

  • Hi John,

    Were you able to do the swap? Did it fix the system or is it still giving you trouble?