Other Parts Discussed in Thread: SN74AHCT1G14, SN74LVC2G17
Hello,
Currently using the SN74LVC1G17 for a high speed delta sigma transmission, my application requires good synchronisation between data and clock.
My issue is the following: for Vcc = 5V the datasheet state 1.2 < tdp < 5 ns. This means that at each buffer stage I get 3.8 ns of uncertainty. Having few stages in series for both data and clock my uncertainty reaches problematics value.
On what parameter depends the tdp value? Does the (tdp_MAX - tdp_MIN) value get reduces for a fixed 5V supply and a fixed load ? If I measure this value, will it change a lot if I use the exact same circuit but use another SN74LVC1G17 chip?
Same question for the SN74AHCT1G14.
Thank you in advance and best regards,
Rémi Freiche