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There are a few issues with trying to determine a maximum capacitive load for a standard CMOS logic device.
First is propagation delay.
Any CMOS logic device is tested at a particular load (typically 15, 30, or 50 pF) for propagation delay. Increasing the load capacitance will linearly increase the propagation delay due to the slowing of the output transition rate. There's an FAQ that goes into detail on output transition rate here: [FAQ] What is the output transition rate for a logic device?
Related to the propagation delay change is the change in input transition rate to the next stage.
Typically a logic device's output will be going to the input of a CMOS device. If the input transition rate to a CMOS device is too slow, it can cause oscillations, excessive current, and possibly damage to the device. This is explained in detail here: Implications of Slow or Floating CMOS Inputs
There are also issues with output drive current.
If you can imagine your load as an infinitely large capacitor, the device will see the output as essentially shorted and short circuit current will flow forever (or until the device is damaged). These logic devices are designed for signal delivery - not power delivery. The general rule of thumb is to keep the output capacitance below 70pF to maintain good operation of the logic device.Channels inside the same device can be paralleled to improve the output driving capacity. For example, an SN74LVC2G34 can have both channels paralleled to drive a 140 pF load with relatively good performance.
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