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Part Number: TXB0304
There is serious reflection showed as attached picture when sending 2MHz clock from TXB0304UTR to xilinx XC3S400AN CPLD through 180mm trace. Tried below experiment but cannot fix the problem:
In the figure, blue wave is the input signal and green wave is the output signal.
figure a, serial resistor vlaue=0Ω
figure b, serial resistor vlaue=50Ω
figure c, serial resistor vlaue=150Ω
figure d, serial resistor not Weld
Watch the Introduction to AXC Family
Read the app note on Glitch-free Power Sequencing for the AXC family
Evaluate the AXC8T245 EVM and watch the translation using the EVM
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In reply to ShreyasRao:
In reply to jian geng:
The Xilinx CPLD has internal pullup pulldown resistors as shown here below. This is causing the low level to not reach zero level.
If there is a way to disable the pullup resistors, it will help the TXB low level go down to zero. The unwanted triggering on the input will also be eliminated due to the smaller voltage level of the signal during low cycle.
Let me know if this can be done.
TXB0104 with 16k pullup
TXB0104 without pullup and ~50pF cap loading.
The slow rising edge is due to the 180mm cable on the output. having larger series resistance will cause to slow down the rise time due to low pass filter.
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