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SN74ALVCH16501: SN74ALVCH16501

Fred Belsak69
Prodigy 40 points
Part Number: SN74ALVCH16501

This is a two-fold question.

1, What is the power-up value of bus hold inputs until driven externally?  What happens when a transceiver is powered-up prior to any output enable?

2, So in the case of a transceiver like the SN74ALVCH16501, if say the A side is driven to the B side, the power-up value of the A-side will appear on the B-side?

  • 0
    TI__Guru* 96591 points
    Hi Fred,
    Each input on a bus-hold transceiver has a weak latch connected to it. These latches typically start in the LOW state, however that is not always the case. There's an application report that goes into details located here: www.ti.com/.../scla015b.pdf

    I'm not 100% sure what you mean on the second question -- a transceiver is basically a direction-controlled buffer. If you have it set to drive from A to B, then the signal input at A will be reproduced at B. The bus-hold circuits are not connected in any way -- they are independent for each I/O pin.
  • 0 in reply to Emrys Maier
    Prodigy 40 points
    Is there a Verilog model for the 74ALVCH16501?
  • 0 in reply to Fred Belsak69
    TI__Guru* 96591 points
    Hi Fred,
    Please forgive my ignorance, but what would be the point of a verilog model of a logic buffer? I've never had a request for one before.

    There are two models available on the website for this device:

    (1) HSpice model - for functional testing

    (2) IBIS model - for signal integrity testing
  • 0 in reply to Emrys Maier
    Prodigy 40 points
    Redirecting responses like these tend to make me less interested in using indirect support resources like this one. Sorry to hear there is no Verilog model.
  • 0 in reply to Fred Belsak69
    TI__Guru* 96591 points
    Hi Fred,
    FYI -- This support forum is as direct as it gets -- you're talking to one of just a handful of electrical engineers that works in Standard Logic for TI. I think a lot of people don't realize this... It's literally part of my job description to make sure I respond to customers just like you within 24 hours of your post and do my best to help. I'm sorry that my initial response didn't have the solution you wanted, but I'm always interested in having a conversation with other engineers and to try to improve.

    I'm genuinely interested to know why you would want a Verilog model for this device - thus why I asked the question in my response.

    Out of thousands of customers and decades of questions, as far as I know, you're the first person to ask. In my experience, Verilog is a great way to model complex digital parts with 4 state logic, however our 'standard logic' devices don't really fall in that category. These devices are digitally very simple, and have many analog performance metrics that wouldn't be represented in a Verilog model -- at least, not in any Verilog model I've ever seen.

    If you have an explanation, then I might be able to build a business case and convince TI that it's worth our time and effort to produce a Verilog model. Without any additional info, I can't really do that, and things won't change. It's people like you that really make the difference for the future of TI & electronics in general. Hopefully you will continue to use these forums to find what you need from Texas Instruments in the future.