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SN74AHC595: The exact voltage of CLK to sample the data

Part Number: SN74AHC595

Hi team,

Because the SRCLK and the RCLK is the positive edged triggered.

Does it triggered in 50% of the edge? The customer want to know the exact voltage for the clk to sample the data.

Do you have the CLK voltage to sample the data?

Lacey

Thanks a lot!

  • Hi Lacey,
    As with all standard CMOS devices, the actual exact transition voltage is irrelevant if the device is being operated correctly. Incorrect operation can cause damage to the device and is not recommended by TI.

    The input MUST transition from in less time than the Δt/Δv spec in the recommended operating conditions. Having an input that is slower than this or one that does not reach the VIH/VIL values given in the datasheet can cause excessive current, oscillations, and damage to the device.

    It is for these reasons that the input threshold voltage for standard CMOS devices is not provided. The input typically switches at 1/2*Vcc -- but this is not really testable due to the issues mentioned above.
  • Hi Emrys,

    So you mean the output change is not sample by the SRCLK, it due to the rising edge of the input?

    If the rising edge and the voltage of the input signal can meet the requirement of the specs, the output will change from low to high, right?

    And then what's the function of the SRCLK and the RCLK? Why do we need to follow the timing as the datasheet notes?

    In customer's application, they test the raising edge of the CLK has some glitch or not sharp, so they want to know if this will cause issue?

    Is there any requirement for the raising time of the CLK, what's the actual function of the SRCLK and RCLK?

    Lacey

    Thanks a lot!

  • Hi Lacey,
    Thanks for posting the scope shots - this clears up the issue very much.

    Since they aren't seeing ringing on the top end (overshoot), and the rise time is very fast, this looks like an issue with the measurement to me. It's very common to see non-monotonic behavior like this when probing a board, especially when the ground of the probe is not connected close to the device under test.

    It's likely that the operational signal does not exhibit this behavior.