This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

SN74LVC8T245-Q1: nOE and Power Sequencing

Prodigy 20 points

Replies: 2

Views: 121

Part Number: SN74LVC8T245-Q1

I see the following note in the SN74LVC8T245-Q1datasheet:

"To ensure the high-impedance state during power up or power down, nOE should be tied to VCC through a pullup resistor"

Is this a requirement even for pins that are designated as inputs via the DIR pin? IE, if DIR is tied to Vcca and nOE is tied low throughout power-up, is there a risk that the A ports will be enabled and back-drive?

What if DIR and nOE are both tied to Vcca as Vcca is brought up, then nOE is pulled low, then Vccb is brought up last? 

  • Hi Joseph and welcome to the forums!
    First, this device has partial-power-down specified (aka I_off), which puts all I/O pins of the device into the high impedance state whenever one (or both) of the supplies is held at 0V. The leakage is specified in the Electrical Characteristics table under the name "Ioff".

    Assuming that the DIR circuitry gets powered up first (the DIR circuitry is referenced to VCCA), then it will correctly determine the direction and prevent the A ports from becoming outputs. Because there are minor variations in the process, it's possible for the outputs to become active before the DIR circuitry, so it is possible for a glitch to occur.

    The OE\ pin is specially designed to activate first and will keep everything high impedance as soon as the required bias voltage is available on the supply pin. If you want to ensure there is no possibility of glitches on startup, holding OE\ high is the only guaranteed method.


    Looking for a low voltage translator? Check out the AXC family that supports 0.7V to 3.3V translation!

    The Logic Minute training page has videos on many interesting topics that all are kept shorter than 5 minutes.

  • In addition to what Emrys pointed out, I would also recommend having the IO ports grounded.
    The input circuitry on the IO ports are always active, hence having floating ports can cause higher Icc current and also possibly could trigger the other port when one of the supply is ramping. having a weak pulldown on the IO ports, will ensure a known voltage.
    What are the voltages being translated?
    Would you consider using SN74AXC8T245-Q1 for up to 3.6V translation? These do not need external pulldown / pullup resistors when the supplies are ramping and is known for no glitch outputs.
    You can also refer to the app note here: www.ti.com/.../scea058a.pdf

    -Thanks,

    Shreyas

    Watch the Introduction to AXC Family

    Read the app note on Glitch-free Power Sequencing for the AXC family

    Evaluate the AXC8T245 EVM and watch the translation using the EVM

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.