Part Number: LSF0204-Q1
Hi We faced an issue for UART_TX level translation that means the voltage level is kept on high always.(A/B side of level shift). It seems like the internal MOS doesn't work normally based on current setting. Current design is to place pull up 10K on B side of level shift only. In this case, we tried to change the pull up reisitance value up to 62Kohm to adjust a capable of driving current. The level shift can be workable but i'm afraid a such higher resistance value will increase the charge time.(Pull up lower than 51Kohm isn't workable) May I have your comments for this? Why the pull up 10Kohm can't turn on for level translation? Your feedback will be appreciated. Thanks. Please find the schematic&waveform for your reference.
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What is the drive strengh of your other chip?
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