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Part Number: SN74LV221A
If we have port A low and we pulse the port B a second time during the discharge of the external capacitor, the output pulse is either shorter than expected, or worse just a single very short pulse! We would expect that the second pulse would be ignored (as it is with HEF4528 and stated in your datasheet). We have an RC of 1nF capacitor and 1.5k resistor. As you may see on the fist attached picture (ptm1), we have the second pulse ignored if it arrives after the full discharge of the capacitor. On the second picture (ptm2), we have the second pulse during the discharge of the capacitor, which reduces the length of the output pulse. On picture three (ptm3) it is even worse, because the output pulse length is the difference between the two input pulses. (note : blue trace is input on pin B, purple trace is capacitor on RX/CX pin, green trace is output Q) If a third pulse arrives, it retriggers the monostable!!! Strange situation for a NON-retriggerable monostable. Please note that the input pulses width (~20ns) are larger than the ones specified in your datasheet (min 5ns). In your datasheet it is written: "Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components". It is clearly not the case! Our "clear" input is still and not noisy, so it cannot come from this source. Do you have an idea on how to overcome this?
Welcome to the forum! Can I get the third scope shot (ptm3) zoomed in on the time scale to 50 ns. Can you also put the one of the markers to monitor the purple trace voltage right when the output pulse stops. I want to see a what voltage the causes the output to stop so I can verify if the issue is with the comparator internal to the device.
Also, have you used another device and witnessed the same issue with the new device placed in the same circuit?
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In reply to Dylan Hubbard:
Here is a zoom on the signals to 50ns/div. The pulses are 15ns long with 54ns between them. This is the maximum delay between the pulses for this phenomenon to appear. The capacitor discharges to 2.6V only.
Once I enlarge to 51ns, the pulse is shorter than expected by the RC ratio, but longer than the difference between the two input pulses as shown here.
Just for fun I tried instead of the initial 1nF capacitor and 1.5k resistor, a capacitor of 10nF to see if the capacitor discharges to the same level of 2.6V. It appears that it only discharges to 3.54V only for the phenomenon to appear (see ptm_10nF picture). The pulses here are 26ns long (no influence on the phenomenon) and the time between the two rising edges is 284ns !!!
In reply to Nicolas Voumard:
We have tested the 74HC221 and 74HCT221 on the same test-bench with the same conditions and they does not react the same way. On those families, the second pulse is clearly ignored as mentioned in the datasheets. However, the propagation delay is bigger (15 - 20 ns more) than the 74LV221. This was the reason why we took the LV family...
Thanks for getting me this scope shot and taking additional data points. I'm ordering some samples of my own so I can try to replicate this as well. I see devices from other families are working fine, but were you able to run a test with a different 74LV221 device?
Yes, we have a whole batch of 250 cards that have the same problem. I have made the same measure on five of them and they all have this problem.
However, all the 74LV221 come from the same batch and I have not tested pieces coming from another batch.
Thanks for those details. I've ordered samples and will set up a test circuit to run some tests of my own. I expect to provide results within a weeks time.
Could I get a schematic of this device so I can replicate it on my test set up?
Sorry for my late answer about the schematic. I can't share the shematic of our design.
However, I have used to test these 74LV221A the simplest circuit possible to check whether it was not our design that caused the problem.
We have used a Tektronix AFG3252 to generate the pulse bursts directly connected to the input of the 74LV221A input B. Input A is tied low and CLR is pulled to VCC (5V).
Both input and output have a pull-down of 10k.
The same circuit works fine with 74HC221, as well as with the 74LV123. With the 74LV221, the pulse seems to be reset if a second pulse arrives during the discharge of the capacitor.
Sorry for my late reply as well, I wanted to give you an update on this. I replicated your schematic on my test set up and ran some tests. I'm seeing similar results as you, so I'm pursuing additional testing variables to see if I can isolate the issue. Bear with me through this process, I will keep you updated with any additional results.
This process will take longer than expected. Can I help you find an alternative part for your system?
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