Part Number: CD4013B
I have been using CD4013 to control ON & OFF of a specific device. The turning OFF/ON is created by giving a positive edge voltage trigger at the clock pin of the IC. The output of the Q bar is connected to the D input, reset is grounded. This logic is working fine for most of the devices.
In some specific cases, the voltage at the clock pin is drifting which is causing the device to automatically ON/OFF. Can you please explain me the happenings of this?
The clock pin is a high-impedance CMOS input. If the voltage is not valid logic level, then either there is something wrong with the circuit that is driving this signal (please show the schematic), or the input has been damaged (probably by ESD or overvoltage).
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In reply to Clemens Ladisch:
We are handling the IC's in an ESD safe environment. Our assumption is that when the IC is assembled on to a board the chances of ESD failures are very less as there can be multiple paths. Is there any chance by which an ESD failure can occur when the IC Is assembled on a PCB?
In reply to Radel Design Team:
The built-in ESD protection is designed to handle ESD that happens during automated assembly. The driving circuit, or overvoltage coming from it, is the much more likely source of the problem. Please show the schematic.
Sorry for the late reply. Here is the schematic :
Unused CMOS inputs must not be left open.
The time constant of the RC filter at the switch is 100 µs. So the rising edge will exceed the trCL limit..
But neither of these is likely to damage the CLK input this way. I'd guess that you are getting ESD when the switch is being touched. Try adding some protection, e.g., series diodes from GND and to VCC, and a resistor in front of CLK.
Thanks Clemens Ladisch!
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