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  • TI Thinks Resolved

Channel-to-Clock Skew clarification

Prodigy 225 points

Replies: 4

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Part Number: TXS02612

Hello,

I am using TXS02612 as SD Card voltage-level translator with a Zynq-7000 Xilinx FPGA. The Xilinx Answer Record AR# 63913 (Zynq - Marginal SDIO timing on ZC702 and ZC706 can lead to data CRC error while initiating write to SD device) advise for a "possible violation of the 2.0ns input hold time as defined in the SDIO specification" when using a voltage-level translator. To resolve this issue, "SD_DAT[0:3] and SD_CMD lines must be lengthened to compensate for the maximum channel skew as specified in the level shifter data sheet". (www.xilinx.com/.../63913.html)

This recommendation is also in the Xilinx Zynq-7000 SoC PCB Design Guide (UG933 - Section MIO/EMIO IP Layout Guidelines - SDIO (v1.13.1 p.68)).

When I look at TXS02612 Datasheet switching characteristics for VCCA=1.8V (Table at p.12), tpd(max) from Port A to Port B for CMD/DAT is not necessarily higher than tpd(max) for CLK.
     - When VCCB=1.8V, tpd(max) for CMD (8ns) and DAT (8.4ns) is smaller than tpd(max) of CLK (9ns).
     - Inversely, when VCCB=3.3V, tpd(max) for CMD (5.7ns) and DAT (5.8ns) is higher than tpd(max) of CLK (4.5ns).


From those characteristics, one could conclude that in some conditions, the buffer Channel-to-Clock skew could be positive (buffer delay higher for CMD/DAT than delay for CLK) and in other conditions, the buffer Channel-to-Clock skew could be negative (buffer delay smaller for CMD/DAT than delay for CLK).

In order to properly compensate for TXS02612 channel skew on PCB:
     - I need to know for VCCA=1.8V/2.5V with VCCB=3.3V, if the Channel-to-Clock skew (tsk(o)) given in the datasheet is always positive i.e. that the buffer delay of CMD/DAT ports is guaranteed to be higher than buffer delay for CLK port?


Thank you.

  • Hello,

    I can only guarantee what is written in the datasheet. If the tpd max of the CMD and DAT line is greater than the tpd of CLK, it doesn't not necessarily mean that the buffer delay of the CLK port will be less than those two channels. The delay can vary from part to part and so for that reason we provide a range that we guarantee all parts on. tpd also varies with temperature and this range accounts for the entire operating temp range of the part.

    Thanks!

    -Karan

  • In reply to Karan Kotadia:

    Thank you,

    For the sake of clarity, if the Channel-to-Clock skew (tsk(o)) given in the datasheet is 1.48ns, it means that CMD/DAT ports to CLK port skew could range anywhere form -1.48ns to +1.48ns? In other words, if CMD/DAT and CLK signals are aligned at buffer input, CMD/DAT signals can be output as much as 1.48ns before or 1.48ns after CLK output?

    If so, to follow the Xilinx recommendation to lengthened DAT/CMD lines to compensate for maximum channel skew (refer to first post for details), DAT/CMD traces should be at least 10 inches (using propagation delay of 150ps/in) longer than CLK trace.

    Thank you.

  • In reply to Nicolas V:

    Hi,

    Can you please confirm the previous statement?

    Thank you.

  • In reply to Nicolas V:

    Hi Nicolas,

    Sorry for the delay, yes that spec indicates that the clock and channel won't be greater than 1.48 ns apart.

    Check out our new AXC family of Voltage Translators! 

    Watch the Introduction to AXC Family to find out more about the family.

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